Gate Spacer Diffusion Barrier for Ge-Safe Metal Gate Replacement
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently while maintaining performance and reliability, particularly in multi-gate devices like FinFETs, due to issues with material selectivity and etch processes.
Innovation Solution
The fabrication method involves forming epitaxial stacks with sacrificial layers of differing compositions, patterning fins, and replacing sacrificial gates with high-K metal gate structures, using UV curing to enhance spacer resistance and etch selectivity, resulting in improved device performance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but material selectivity and etch process control deteriorate
Solution Approach 1:
The patent applies local quality by forming a first material layer with different etch selectivity than the second material layer, allowing selective etching of the first material layer while preserving the second material layer. This local differentiation in material properties enables precise control at the nanoscale level, resolving the contradiction between reduced feature size and maintained manufacturing precision.
Solution Approach 2:
The patent changes material parameters by selecting materials with different etch selectivities for the first and second material layers. By adjusting the etch selectivity parameter through material selection, the process achieves both high integration density and precise etch control, allowing selective removal of sacrificial layers without affecting adjacent structures.
2Productivity
If feature size is reduced to improve integration density, then more components fit in given area, but device performance and reliability deteriorate
Solution Approach 1:
The patent uses local quality by implementing different material properties in different regions - the first material layer has high etch selectivity for sacrificial layer removal, while the second material layer maintains structural integrity. This localized material differentiation allows aggressive etching where needed while preserving device performance in critical regions.
Solution Approach 2:
The patent employs composite materials by combining multiple material layers with different properties - a first material layer optimized for selective etching and a second material layer optimized for structural support and device performance. This composite approach enables both high integration density and maintained reliability through functional specialization of each layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and reliability of multi-gate devices by improving material selectivity and etch processes, leading to better device performance and reduced leakage.
Implementation Method 1
the first material layer blocks Ge from entering the metal gate
Implementation Method 2
performing, on a first material layer including the gate spacer layer, treatment operations that are configured to make the first material layer more resistant to Germanium (Ge) penetration
Data Source
AI summary
A fabrication method, includes: forming a gate spacer layer around a sacrificial gate structure disposed over a substrate; performing, on a first material layer that includes the gate spacer layer, treatment operations that are configured to make the first material layer more resistant to Germanium (Ge) diffusion during metal gate replacement operations; forming a second material layer adjacent to the first material layer; and replacing the sacrificial gate structure with a metal gate, wherein the first material layer blocks Ge from entering the metal gate.