Gate Dielectric Spacer Layout for Lower GIDL in MV Transistors
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Solution Overview
Problem
Conventional polysilicon gates in semiconductor devices suffer from boron penetration and depletion effects, leading to increased equivalent thickness of the gate dielectric layer and reduced gate capacitance, which worsens driving force and results in gate-induced-drain-leakage (GIDL) issues, particularly in medium-voltage (MV) devices with closely spaced doped regions.
Innovation Solution
A method involving the formation of a gate dielectric layer, a gate electrode, first and second spacers, and source/drain regions, where the second spacer is used as a mask to remove part of the gate dielectric layer, creating inclined sidewalls to prevent doped regions from being too close to the gate electrode, thereby reducing GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If doped regions are placed close to the gate electrode to improve device integration, then device density increases, but gate-induced-drain-leakage (GIDL) increases
Solution Approach 1:
The invention divides the gate dielectric layer into two distinct regions: a first gate dielectric layer directly under the gate electrode, and a second gate dielectric layer in the drain region. This segmentation allows the drain region to have adequate dielectric coverage for preventing GIDL while maintaining high device integration density through optimized spacing and structure.
Solution Approach 2:
The invention introduces an intermediary structure (the patterned gate dielectric layer configuration with spacers) between the gate electrode and the doped drain regions. This intermediary arrangement physically separates the gate from the doped regions while maintaining electrical control, thereby reducing GIDL without sacrificing integration density.
2Ease of manufacture
If polysilicon is used as gate material to simplify fabrication, then manufacturing complexity decreases, but boron penetration and depletion effects increase
Solution Approach 1:
The invention employs a composite gate structure combining a metal gate electrode with a high-k gate dielectric layer. This composite material approach eliminates boron penetration and depletion effects inherent in polysilicon gates while maintaining fabrication compatibility through the structured dielectric layer arrangement and spacer formation processes.
3Object-generated harmful factors
If the gate dielectric layer is removed partially to reduce GIDL, then leakage decreases, but gate capacitance may be reduced
Solution Approach 1:
The invention applies local quality by having different gate dielectric layer configurations in different regions: the first gate dielectric layer maintains full coverage under the gate electrode to preserve gate capacitance, while the second gate dielectric layer in the drain region provides necessary coverage to prevent GIDL. This localized differentiation optimizes both capacitance and leakage performance.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate electrode on the gate dielectric layer, forming a first spacer adjacent to the gate electrode, forming a lightly doped drain (LDD) in the substrate adjacent to the first spacer, forming a second spacer adjacent to the first spacer, removing part of the gate dielectric layer, and then forming a source/drain region in the substrate.