Gate Spacer Isolation for Semiconductor Short-Circuit Bridging
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Solution Overview
Problem
As semiconductor device scaling down continues, challenges in fabrication arise, including increased risks of bridging or electrical shorting problems that degrade device performance or cause failures, which existing semiconductor fabrication methods have not adequately addressed.
Innovation Solution
The method involves forming a semiconductor device with a substrate, fins, gate structures, gate spacers, and hard masks, where the gate helmets are formed over the gate structures, and conductive contacts are created with spacers and hard masks to enhance isolation and reduce the risk of short-circuit bridges, using processes like photolithography and etching to achieve precise dimensions and material selection for etching selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device scaling down continues to increase functional density, then the number of interconnected devices per chip area increases, but the risk of bridging or electrical shorting problems increases
Solution Approach 1:
The patent divides the gate structure into multiple segments by forming gate spacers on opposite sidewalls of the gate structure. These gate spacers create isolated regions that prevent electrical shorting between adjacent conductive contacts while maintaining high functional density through compact layout
Solution Approach 2:
The patent introduces gate spacers as intermediary structures between the gate structure and conductive contacts. These spacers act as protective barriers that prevent direct contact between potentially shorting elements, thereby reducing bridging risk while allowing continued device scaling
2Area of moving object
If geometry size decreases to create smaller components, then more complex circuits fit on chip area, but fabrication challenges increase
Solution Approach 1:
The patent performs preliminary patterning actions by forming mandrels and gate structures before creating conductive contacts. This sequential approach with pre-defined patterns simplifies subsequent fabrication steps and reduces manufacturing complexity despite smaller geometry sizes
Solution Approach 2:
The patent utilizes etching selectivity between different materials (gate dielectric layer vs. other layers) to achieve precise patterning at small dimensions. By controlling etching parameters and material properties, the patent enables accurate feature formation with reduced fabrication challenges
3Reliability
If critical dimensions are increased to reduce capacitive resistance, then device performance improves, but chip area increases
Solution Approach 1:
The patent extends the gate spacers vertically along the sidewalls of the gate structure, utilizing the vertical dimension to increase the effective isolation length without proportionally increasing horizontal chip area. This three-dimensional approach allows improved device performance with compact footprint
Data Source
AI summary
A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.