Semiconductor Gate Structure Sidewall Spacer Leakage Current
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Solution Overview
Problem
Conventional semiconductor device fabrication methods result in poor electrical performance due to leakage current issues caused by the exposure of upper corners of the gate structure during the formation of contact holes, primarily because the etching selectivity ratio between the interlayer dielectric layer and the first sidewall spacer is low, leading to severe etching loss and conduction problems.
Innovation Solution
The method involves forming a semiconductor device with a gate structure and sidewall spacers made of different materials, where a second sidewall spacer is created by removing a portion of the initial sidewall spacer, forming a trench, and a second protective layer is deposited in the trench, ensuring the second protective layer and first sidewall spacer are made of the same material to enhance electrical isolation and prevent upper corner exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-material sidewall spacer is used, then the fabrication process is simple, but the electrical isolation is insufficient leading to leakage current
Solution Approach 1:
The sidewall spacer is segmented into two distinct parts: a first sidewall spacer made of a first material and a second sidewall spacer made of a second material. This segmentation allows each part to perform different functions - the first sidewall spacer provides structural support while the second sidewall spacer provides enhanced electrical isolation, thereby resolving the contradiction between fabrication simplicity and electrical isolation performance.
Solution Approach 2:
The patent employs composite materials by combining two different materials in the sidewall spacer structure. The first material and second material are selected to have complementary properties, where one provides mechanical stability and the other provides superior electrical isolation. This composite approach enables the structure to simultaneously achieve both ease of manufacture and high reliability in electrical isolation.
2Ease of operation
If the etching selectivity ratio between interlayer dielectric layer and sidewall spacer is low, then the etching process is easier to control, but severe etching loss occurs exposing upper corners of gate structure
Solution Approach 1:
The patent changes the material parameter of the sidewall spacer by using a second material with different etching characteristics. This material parameter change increases the etching selectivity ratio between the interlayer dielectric layer and the second sidewall spacer, allowing the etching process to selectively remove the interlayer dielectric layer without excessively eroding the sidewall spacer and exposing the upper corners of the gate structure.
Solution Approach 2:
The second sidewall spacer acts as an intermediary protective layer between the etching process and the gate structure. By introducing this intermediate layer with superior etching resistance, the patent protects the upper corners of the gate structure during etching while still allowing the etching process to proceed with acceptable controllability.
3Productivity
If contact hole size decreases with smaller gate structure spacing, then device density increases, but lithographic limitations are reached
Solution Approach 1:
The patent implements a self-aligned contact hole formation process where the second sidewall spacer automatically defines the contact hole position and dimensions. The self-service mechanism eliminates the need for separate lithographic patterning steps for contact holes, allowing contact holes to be formed with precision determined by the sidewall spacer geometry rather than lithographic limitations. This enables continued increase in device density without hitting lithography walls.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical performance of the semiconductor device by preventing the exposure of upper corners of the gate structure, thereby reducing leakage current and enhancing the overall performance by combining the advantages of different material properties in the sidewall spacer structure.
Implementation Method 1
forming a second protective layer in the trench, the second protective layer and the first sidewall spacer being made of the same material
Data Source
AI summary
A semiconductor device and a fabrication method are provided. The fabrication method includes providing a gate structure on a substrate and a first protective layers on the gate structure; forming an initial sidewall spacer on a sidewall of each of the gate structure and the first protective layer; forming a first sidewall spacer on a sidewall of the initial sidewall spacer, the first and initial sidewall spacers being made of different materials; forming a second sidewall spacer by removing a portion of the initial sidewall spacer, leaving a trench formed above the second sidewall spacer and between the first sidewall spacer and the first protective layer; and forming a second protective layer in the trench, the second protective layer and the first sidewall spacer being made of a same material. The second sidewall spacer has a top surface higher than or level with a top surface of the gate structure.