Semiconductor Gate Spacer and Liner for Carrier Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming stressor regions in semiconductor devices, such as MOSFETs, are not entirely satisfactory in enhancing carrier mobility and device performance, particularly as devices are scaled down in technology nodes.
Innovation Solution
A method for fabricating semiconductor devices involves forming dummy gate structures, liner layers, spacers, and interlayer dielectrics, followed by the removal of dummy gates to create openings for metal gates, which includes specific etching processes and spacer formations to enhance device performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods for forming stressor regions are used, then device fabrication is simplified, but carrier mobility and device performance are not sufficiently enhanced
Solution Approach 1:
The fabrication process is divided into distinct stages: forming mandrel structures, depositing first spacers, creating recesses, forming second spacers, and removing mandrels. Each stage performs a specific function, allowing precise control over stressor region formation while maintaining overall process manageability despite increased complexity
Solution Approach 2:
Mandrel structures are formed in advance as templates before the actual stressor regions are created. These preliminary mandrels guide the subsequent spacer formation and material deposition processes, ensuring accurate positioning and dimensions of the final stressor regions
2Productivity
If device geometry is scaled down, then production efficiency increases and costs decrease, but processing complexity increases
Solution Approach 1:
The spacer structures self-align to the mandrel features through conformal deposition, automatically defining their positions and dimensions based on the mandrel geometry. This self-service mechanism reduces the need for additional alignment steps and complex processing controls, enabling scaling while managing complexity
3Reliability
If stressor regions are formed to enhance carrier mobility, then device performance improves, but leakage paths increase
Solution Approach 1:
The spacer structures provide localized stress enhancement precisely at the stressor regions while maintaining different material properties and structural characteristics in adjacent areas. This local quality differentiation allows stress-induced mobility enhancement without creating unwanted leakage paths in other regions
Solution Approach 2:
The spacer structures act as intermediary elements between the stressor regions and the surrounding device structures. They mediate the stress distribution and provide structural isolation, enabling carrier mobility enhancement while preventing leakage paths from forming between adjacent device regions
Data Source
AI summary
A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate.