Gate Spacer Structure for Low-Capacitance Semiconductor Contacts
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with parasitic capacitance and device integrity.
Innovation Solution
The method involves forming air spacers and second spacers with specific etching selectivity to protect underlying components during contact hole formation, reducing parasitic capacitance and enhancing device performance by using a sequence of spacer layers and sacrificial materials to maintain structural integrity and reduce device height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process difficulty increases and device reliability deteriorates
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming first spacers around gate stacks, removing portions of interlayer dielectric, forming second spacers, and creating contact holes. This segmentation allows each step to be optimized independently, maintaining reliability while enabling smaller feature sizes.
Solution Approach 2:
Air spacers and second spacers are formed in advance before contact hole formation. These spacers are positioned to protect underlying components during subsequent etching processes, ensuring device integrity is maintained even as feature sizes decrease.
2Device complexity
If conventional spacer formation methods are used, then process simplicity is maintained, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
Air spacers are formed by removing material to create void spaces between the gate stack and conductive structures. This extraction of material eliminates dielectric regions that would otherwise contribute to parasitic capacitance, directly addressing the harmful effect while maintaining a relatively simple process flow.
Solution Approach 2:
The structure employs a composite approach combining different materials: air (vacuum) as the spacer material to minimize capacitance, surrounded by protective dielectric layers (interlayer dielectric and spacer materials). This composite structure achieves low parasitic capacitance while providing necessary mechanical support and processability.
3Ease of manufacture
If contact holes are formed without protective spacers, then manufacturing steps are reduced, but underlying components are damaged and device integrity is compromised
Solution Approach 1:
Air spacers and second spacers serve as intermediary protective structures during contact hole formation. These spacers are positioned between the etch process and the underlying gate stack, mediating the interaction to prevent direct damage while allowing controlled formation of contact holes. The spacers can be selectively removed after serving their protective function.
Data Source
AI summary
A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.