Gate Spacer Margin for Semiconductor Fabrication

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Solution Overview

Problem

As semiconductor devices are miniaturized, insufficient margins of gate spacers on dummy gates lead to defects such as nodule defects, necessitating a method to ensure reliable fabrication with a sufficient gate spacer margin.

Innovation Solution

A method involving the formation of a dummy gate with an interlayer oxide layer and a dummy gate mask, followed by the creation of a gate spacer that covers the dummy gate and interlayer oxide layer, and subsequent epitaxial growth within a recess, ensuring a sufficient spacer thickness to prevent nodule defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If device size is scaled down to increase integration, then device density improves, but gate spacer margin becomes insufficient leading to nodule defects

Engineering Contradiction:
Improvedevice areaVSAvoidgate spacer margin
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The gate spacer formation process is segmented into multiple stages: initial gate spacer formation, dummy gate mask formation with oxide layer, and additional gate spacer formation. This segmentation allows each stage to contribute to the total gate spacer width, ensuring sufficient margin even as device size scales down.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The oxide layer is formed on the dummy gate before gate spacer formation, serving as a preliminary structure that defines the gate spacer width. This preliminary action ensures that the gate spacer will have adequate margin from the dummy gate, preventing nodule defects in subsequent processing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If gate spacer margin is increased to prevent nodule defects, then manufacturing reliability improves, but device integration density decreases

Engineering Contradiction:
Improveprocess reliabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The gate spacer structure is divided into multiple components formed at different stages, allowing the total gate spacer width to be sufficient for reliability while maintaining compact device layout through efficient space utilization of each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate spacer width is controlled not only in the lateral dimension but also through vertical layering with the oxide layer and dummy gate mask, allowing sufficient margin in three-dimensional space while maintaining planar device density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If multiple layers (oxide layer and dummy gate mask) are formed on dummy gate, then gate spacer protection is improved, but fabrication process complexity increases

Engineering Contradiction:
Improvegate spacer protectionVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The oxide layer and dummy gate mask serve multiple functions: they define gate spacer width, protect the dummy gate during etching, and serve as etch stop layers. This multi-functionality justifies the additional layers despite increased process steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The oxide layer acts as an intermediary between the dummy gate and the gate spacer, providing a controlled interface that ensures proper gate spacer formation and protection while simplifying the overall process control compared to direct gate spacer formation on the dummy gate.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances process reliability by preventing nodule defects and ensuring the gate spacer serves as a protective layer during epitaxial growth, improving the operational performance and yield of semiconductor devices.

Implementation Method 1

forming an oxide layer and a dummy gate mask layer on the dummy gate

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

forming an epitaxial layer in the recess using an epitaxial growth process

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS9653572B2Method for fabricating semiconductor device
Publication Date: 2017.05.16 SAMSUNG ELECTRONICS CO LTD
  • US9653572B2 patent drawing
  • US9653572B2 patent drawing
  • US9653572B2 patent drawing

AI summary

A method of fabricating a semiconductor device includes forming a dummy gate on a substrate, forming a dummy gate mask on the dummy gate, forming a gate spacer on the substrate, the gate spacer covering at least one sidewall surface of the dummy gate and the dummy gate mask, forming a recess on at least one side of the dummy gate by etching the substrate, and forming an epitaxial layer in the recess using an epitaxial growth process. The forming of the dummy gate mask includes forming an oxide layer and a dummy gate mask layer on the dummy gate.