Gate Spacer Tuning for Medium-Voltage Integrated Transistors
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Solution Overview
Problem
The existing manufacturing of integrated circuits lacks cost-effective and optimized transistors configured for medium-voltage ranges, as high-voltage transistors are typically used due to cost constraints, resulting in suboptimal performance and excessive bulk due to their design for high voltages.
Innovation Solution
A method involving the formation of gate regions on a semiconductor substrate, deposition of dielectric layers to form spacers, and selective etching to reduce spacer width, allowing for optimized lightly doped and strongly doped conduction regions, which reduces hot carrier phenomena and parameterizes the threshold voltage for improved performance in medium-voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high-voltage transistor architecture is used for medium-voltage operation, then cost is reduced by reusing manufacturing steps, but performance is suboptimal and device bulk is excessive
Solution Approach 1:
The patent applies local quality by creating different spacer widths for different transistor types on the same substrate. Medium-voltage transistors have reduced spacer widths (w1) while high-voltage transistors maintain larger spacer widths (w2). This is achieved through selective etching that removes dielectric layers only in medium-voltage transistor regions, allowing each transistor type to have optimized dimensions for its specific voltage requirements while using the same base manufacturing process
Solution Approach 2:
The patent changes the physical parameter of spacer width to optimize transistor performance for different voltage ranges. By controlling the width of dielectric layers adjacent to the gate region, the patent adjusts the electrical characteristics of transistors. Medium-voltage transistors receive reduced spacer widths through selective removal of dielectric material, while high-voltage transistors retain larger spacer widths, thereby tuning the electrical parameters without requiring completely different manufacturing processes
2Ease of manufacture
If high-voltage transistor architecture is used for medium-voltage operation, then manufacturing steps are reused, but device compactness is reduced due to excessive bulk
Solution Approach 1:
The patent implements local quality by spatially differentiating the spacer dimensions across the substrate. Medium-voltage transistors are assigned reduced spacer widths (w1) while high-voltage transistors maintain larger spacer widths (w2). The selective etching process removes dielectric material specifically in medium-voltage transistor regions, enabling compact device dimensions where needed while preserving the larger dimensions required for high-voltage transistors, all within a unified manufacturing framework
Solution Approach 2:
The patent applies partial action by selectively removing dielectric layers only in the regions corresponding to medium-voltage transistors, rather than uniformly across the entire substrate. This partial removal achieves the necessary compactness for medium-voltage devices without affecting high-voltage transistor regions, which require the full spacer width for proper operation. The etching process is precisely targeted to achieve the desired dimensional reduction only where needed
3Ease of manufacture
If standard spacer width is used for medium-voltage transistors, then manufacturing is simplified, but hot carrier phenomena increase causing degradation
Solution Approach 1:
The patent applies local quality by creating differentiated spacer widths tailored to specific transistor voltage requirements. Medium-voltage transistors receive reduced spacer widths (w1) through selective etching that removes dielectric material only in their regions, while high-voltage transistors maintain larger spacer widths (w2). This localized dimensional optimization reduces hot carrier phenomena in medium-voltage transistors without complicating the overall manufacturing process, as the differentiation is achieved through a single selective etching step integrated into the existing fabrication sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of transistors optimized for medium-voltage ranges with reduced hot carrier degradation and tailored threshold voltage, enhancing performance while maintaining cost-effectiveness by reusing manufacturing steps from high-voltage transistor production.
Implementation Method 1
depositing dielectric layers accumulating on the sides of the first gate region so as to form regions of spacers
Implementation Method 2
depositing dielectric layers accumulating on the sides of the first gate region so as to form regions of spacers
Implementation Method 3
performing a first step of implantation of dopants aligned on the regions of spacers to form first lightly doped conduction regions of the first transistor; and performing a second step of implantation of dopants to form first conduction regions of the first transistor
Data Source
AI summary
An integrated circuit includes transistor. That transistor is manufactured using a process including the following steps: forming a first gate region; depositing dielectric layers accumulating on sides of the first gate region to form regions of spacers having a width; etching to remove a part of the deposited dielectric layers accumulated on the sides of the first gate region to reduce the width of the regions of spacers; performing a first implantation of dopants aligned on the regions of spacers to form first lightly doped conduction regions of the transistor; and performing a second implanting of dopants to form first more strongly doped conduction regions of the transistor.