Gate Spacer Offset Layer for MOS Transistor Dimension Control
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Solution Overview
Problem
The challenge in manufacturing advanced MOS transistors is the degradation of gate performance due to high aspect-ratio gate electrodes, which constrain implantation angles and lead to deviations in gate dimensions during the replacement gate process, affecting the formation of LDD and pocket regions and resulting in hot carrier and short channel effects.
Innovation Solution
A gate spacer structure with an offset layer is introduced, allowing for broader implantation angles and maintaining desired gate dimensions by complementing the replacement gate with an offset layer and using a carbon-free etch-stop layer to prevent over-etching, ensuring precise control over the gate stack dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high aspect-ratio gate electrodes are used, then functional density increases, but implantation angles are constrained and gate dimension control deteriorates
Solution Approach 1:
The gate structure is segmented into multiple components: a sacrificial gate electrode, a gate spacer, and an offset layer. This segmentation allows each component to perform its specific function independently, enabling precise control of the final gate dimensions while maintaining high functional density through the compact design
Solution Approach 2:
The gate spacer acts as an intermediary element between the sacrificial gate electrode and the final metal gate. It defines the gate width and provides a template for metal gate deposition, enabling precise dimension control. The offset layer serves as another intermediary that compensates for dimensional deviations and ensures accurate gate stacking
2Reliability
If replacement gate process is used, then metal gate performance is improved, but gate dimension deviations occur during processing
Solution Approach 1:
The gate spacer and offset layer are formed in advance before the metal gate deposition. These preliminary structures serve as precise templates and compensation layers that pre-establish the desired gate dimensions, preventing dimensional deviations during the subsequent metal gate formation process
Solution Approach 2:
The offset layer introduces a controlled dimensional parameter change to compensate for expected shrinkage or expansion during metal gate deposition. By adjusting the offset layer thickness, the final gate dimensions can be precisely controlled despite variations in the replacement gate process
3Ease of manufacture
If broader implantation angles are needed, then LDD and pocket region formation is improved, but gate aspect ratio constraints worsen
Solution Approach 1:
The gate spacer serves as an intermediary structure that decouples the implantation process from the final gate dimensions. During ion implantation for LDD and pocket regions, the sacrificial gate electrode provides masking, allowing broader implantation angles. The gate spacer then defines the precise gate width in the final structure, eliminating the constraint between implantation angles and gate aspect ratio
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacture of MOS transistors with well-controlled gate stack dimensions, improving performance by reducing hot carrier and short channel effects and maintaining critical gate dimensions, even at the 20 nm node or beyond.
Implementation Method 1
using a carbon-free etch-stop layer to prevent over-etching
Implementation Method 2
depositing a dielectric layer on sidewalls of the gate
Data Source
AI summary
A method includes: forming a gate over a semiconductor substrate; forming doped regions in the semiconductor substrate; depositing a dielectric layer on sidewalls of the gate, the dielectric layer including vertical portions laterally surrounding a sidewall of the gate; depositing a spacer laterally surrounding the dielectric layer, the spacer including a carbon-free portion laterally surrounding the vertical portions of the dielectric layer and a carbon-containing portion laterally surrounding the carbon-free portion; forming source/drain regions in the semiconductor substrate; performing an etching operation to remove the gate and vertical portions of the dielectric layer using the carbon-free portion as an etching stop layer to thereby expose the carbon-free portion and form a recess; and forming a gate dielectric layer and a conductive layer in the recess, wherein the gate dielectric layer extends in at least a portion of an area where the vertical portions of the dielectric layer are etched.