Gate Spacer Oxidation for Dielectric and Etch Resistance Balance

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Solution Overview

Problem

As the minimum feature sizes in semiconductor devices are reduced, there is a need to improve the trade-off between the dielectric constant and the etch resistance of gate spacers in FinFETs, which is challenging due to the limitations in tuning the carbon and nitrogen concentrations in these spacers.

Innovation Solution

A multi-step oxidation process is performed on the gate spacer, involving a dry oxidation process followed by a wet oxidation process, to effectively tune the carbon and nitrogen concentrations, thereby improving the trade-off between the dielectric constant and the etch resistance of the gate spacer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the carbon and nitrogen concentrations in the gate spacer are increased to improve etch resistance, then the etch resistance is improved, but the dielectric constant increases which is undesirable

Engineering Contradiction:
Improveetch resistanceVSAvoiddielectric constant
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The oxidation process is segmented into multiple sequential steps (dry oxidation followed by wet oxidation) rather than using a single oxidation step. This allows different oxidation conditions to be applied at different stages, enabling precise control over the chemical composition and concentration of carbon and nitrogen in the gate spacer, thereby optimizing both etch resistance and dielectric constant

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The oxidation parameters (temperature, time, oxidation atmosphere) are changed and optimized across multiple steps. By controlling the oxidation conditions sequentially, the carbon and nitrogen concentrations are precisely tuned to achieve the desired balance between etch resistance and dielectric constant, resolving the contradiction between these two properties

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but additional problems arise in fabricating and controlling gate spacer properties

Engineering Contradiction:
Improveintegration densityVSAvoidfabrication complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The fabrication process is segmented into discrete, controllable steps with the multi-step oxidation process being a key segment. This segmentation allows for precise control of gate spacer properties even at reduced feature sizes, managing the fabrication complexity that arises from miniaturization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate spacer is formed with optimized carbon and nitrogen concentrations through preliminary multi-step oxidation before subsequent fabrication steps. This preliminary optimization of material properties simplifies later fabrication processes and helps manage the overall device complexity associated with reduced feature sizes

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The multi-step oxidation process allows for precise control of the carbon and nitrogen concentrations in the gate spacer, resulting in improved dielectric properties and etch resistance, which enhances the performance and reliability of FinFETs.

Implementation Method 1

performing a multi-step oxidation process to the spacer layer, which includes performing a dry oxidation process and performing a wet oxidation process

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

performing a multi-step oxidation process to the spacer layer, which includes performing a dry oxidation process and performing a wet oxidation process

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS12336249B2Gate spacer and formation method thereof
Publication Date: 2025.06.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12336249B2 patent drawing
  • US12336249B2 patent drawing
  • US12336249B2 patent drawing

AI summary

A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.