Semiconductor Gate Spacer Patterning for Stress Concentration
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Solution Overview
Problem
The increasing integration and miniaturization of semiconductor devices lead to increased electrical resistance in MOS transistors, particularly in gate electrodes and source/drain regions, due to the short channel effect, which affects signal transmission speed and device performance, and existing silicidation processes using metals like cobalt and nickel face processing difficulties and junction leakage issues during gate spacer removal.
Innovation Solution
A method of manufacturing semiconductor devices involving the formation of isolation regions, gate electrodes, and spacer structures with specific layering and patterning of silicon oxide and nitride spacers to concentrate stress on the channel region, while simultaneously removing upper portions of the gate and spacer structures to prevent over-etching and junction leakage, thereby improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate spacer is removed by a dry etching process to obtain stress layer effect, then the transmission speed can be increased, but the active region may be attacked by the etch causing source/drain region to become over-etched and junction leakage to occur
Solution Approach 1:
The patent introduces an intermediary material layer (such as a sacrificial layer or protective coating) between the etching process and the active region. This intermediary layer allows the etch to remove the gate spacer effectively for stress concentration while protecting the active region from over-etching, thus preventing junction leakage while maintaining transmission speed improvement
Solution Approach 2:
The patent applies different protective measures to different regions: the gate spacer is completely removed from the channel region to concentrate stress and improve transmission speed, while the active region is protected through selective masking or protective layers to prevent over-etching and junction leakage. This local differentiation resolves the contradiction between speed improvement and reliability
2Speed
If sufficient etching is required to remove the gate spacer to obtain stress layer effect, then the transmission speed can be enhanced, but the active region can become over-etched and device performance can be limited
Solution Approach 1:
A protective intermediary layer is introduced that allows aggressive etching conditions to be used for complete gate spacer removal while preventing damage to the active region. This mediator enables sufficient etching depth for stress concentration without compromising manufacturing precision
Solution Approach 2:
The patent applies protective layers or masking structures before the etching process begins. This preliminary action prepares the structure to withstand the necessary etching depth for complete gate spacer removal while preventing over-etching of the active region, thus maintaining both transmission speed enhancement and manufacturing precision
Data Source
AI summary
Isolation regions are formed on a substrate to define an active region. A gate electrode is formed on the active region. A spacer structure is formed on a sidewall of the gate electrode. A gate silicide layer is formed on the gate electrode and a source/drain silicide layer is formed on the active region adjacent to the gate electrode. An upper portion of the gate silicide layer and a portion of the spacer structure are simultaneously removed to form a spacer structure pattern and a gate silicide layer pattern. A stress layer is formed to cover the gate electrode and spacer structure pattern.