Replacement Gate Spacer Plasma Etch for Void-Reduced FinFET Filling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices undergo miniaturization, the high aspect ratio of gate cavities in FinFET devices leads to challenges in filling these cavities with gate dielectric and electrode layers, often resulting in the formation of voids or seams that degrade the performance by increasing resistance and causing delays.

Innovation Solution

A plasma treatment is applied to the spacer sidewalls within the gate cavity, altering the material composition and allowing for deeper penetration at the top portions, which upon removal widens the cavity opening, facilitating the deposition of gate dielectric and electrode layers with reduced voids or seams.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the gate cavity has a high aspect ratio due to miniaturization, then the integration density is improved, but the filling process becomes difficult and voids or seams form

Engineering Contradiction:
Improveintegration densityVSAvoidfilling quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies plasma treatment to modify the chemical composition and surface properties of the spacer material. This changes the etch selectivity parameters, allowing the etch process to remove spacer material more effectively at the top of the cavity while preserving the bottom portion, thereby widening the cavity opening and improving fillability without compromising integration density

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The plasma treatment is performed as a preliminary step before the etch process to pre-modify the spacer material. This preliminary action creates a composition gradient in the spacer that facilitates selective removal during subsequent etching, enabling better cavity opening Widening to accommodate gate electrode filling while maintaining the high aspect ratio structure

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the spacer is removed completely to widen the cavity opening, then the filling process is improved, but the gate structure stability deteriorates

Engineering Contradiction:
Improvecavity opening widthVSAvoidgate structure stability
Core Design Contradiction:
Manufacturing precisionVSStrength

Solution Approach 1:

The plasma treatment creates a local quality difference in the spacer material by modifying only the upper portion's chemical composition. This localized modification allows selective etching of the top spacer region to widen the cavity opening while leaving the bottom spacer portion intact to maintain structural stability and support the gate electrode during fabrication

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The spacer removal process is segmented into two zones: the upper portion is selectively removed through plasma treatment and etching to widen the cavity, while the lower portion is preserved to provide structural support. This segmentation enables both cavity widening for better filling and structural stability for gate support

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the filling process, reducing voids and seams, thereby improving the performance of the gate structure by lowering resistance and increasing manufacturing yields.

Implementation Method 1

performing a plasma treatment on portions of the spacer, where the plasma treatment causes a material composition of the portions of the spacer to change

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Data Source

PatentUS11908695B2Replacement gate methods that include treating spacers to widen gate
Publication Date: 2024.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11908695B2 patent drawing
  • US11908695B2 patent drawing
  • US11908695B2 patent drawing

AI summary

A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.