Gate Sidewall Spacer Removal in CMOS Fabrication
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Solution Overview
Problem
The downscaling of CMOS technologies poses challenges in maintaining performance and reliability due to increased channel resistance and junction/contact parasitic resistances, which are exacerbated by gate sidewall spacers that can impede integration density and damage metal silicide structures.
Innovation Solution
A method for removing sidewall spacers from gate structures in CMOS fabrication processes using a conformal insulating layer and etch mask techniques to selectively etch the spacers without damaging the metal silicide layers, allowing for subsequent process flows without impairing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate sidewall spacers are used as masks for ion implantation and salicidation, then ion implantation and salicidation processes are optimized, but the spacers impede integration density and can damage metal silicide structures
Solution Approach 1:
The patent removes the gate sidewall spacers after they have served their masking function in ion implantation and salicidation processes. This extraction of the spacer structures eliminates their harmful effects on integration density and metal silicide structures while preserving the benefits of their temporary presence during critical process steps.
Solution Approach 2:
The spacers are formed in advance to enable precise ion implantation and salicidation processes, then subsequently removed. This preliminary action allows the spacers to perform their masking function before being eliminated to prevent interference with later high-density integration steps.
2Manufacturing precision
If gate sidewall spacers are used to control ion implantation profiles, then dopant profile precision is improved, but the spacers increase gate stack width and narrow spacing between adjacent transistors
Solution Approach 1:
The spacers are removed after serving their precision control function during ion implantation. This extraction eliminates the additional width they contribute to the gate stack, thereby increasing the spacing between adjacent transistor gates and enabling higher integration density.
Solution Approach 2:
The spacers are temporarily formed to establish precise dopant profiles during ion implantation, then removed afterward. This preliminary use allows accurate doping control without the permanent presence of spacers that would constrain device spacing.
3Ease of manufacture
If conventional etch processes are used to remove sidewall spacers, then spacer removal is achieved, but metal silicide structures are damaged
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary between the etch process and the metal silicide structures. This oxide layer absorbs the etch attack, protecting the silicide structures from damage while allowing effective removal of the nitride spacers through selective etching.
Solution Approach 2:
The sacrificial oxide layer is formed in advance to cushion and protect the metal silicide structures during the spacer removal etch process. This protective layer prevents direct contact between the etchant and the silicide, eliminating damage while enabling complete spacer removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively removes sidewall spacers while protecting metal silicide structures, enhancing integration density and maintaining device performance by preventing etch damage and unwanted stresses, thus supporting higher integration density and performance in CMOS devices.
Implementation Method 1
forming a conformal insulating layer over the gate structure and the active silicon region
Implementation Method 2
etching the second spacer insulating layers using an etch process in which an etch selectivity of material forming the second spacer insulating layer is greater than that an etch selectivity of materials forming the first spacer insulating layers and the conformal insulating layer
Data Source
AI summary
Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.