Gate Spacer Removal for Shadowing Mitigation in IC Fabrication
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Solution Overview
Problem
As technology nodes shrink, the high aspect ratio between gate stacks in integrated circuit designs leads to shadowing effects during the formation of pocket/lightly doped source/drain regions, affecting the pocket/LDD formation process, particularly at 22-nanometer technology nodes and beyond.
Innovation Solution
A method for fabricating integrated circuit devices that involves forming gate structures with a narrower line width than the target width, which increases the spacing between gate stacks, thereby reducing the aspect ratio and mitigating shadowing effects during tilt-angle implantation processes, and includes the use of high-k dielectric layers and metal gate electrodes to improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between gate stacks is decreased to shrink technology nodes, then device integration density is improved, but shadowing effects occur during tilt-angle implantation processes
Solution Approach 1:
The patent divides the gate structure formation into multiple stages: first forming gate structures at a narrower line width to increase spacing, then using spacer deposition and removal to achieve the final target width. This segmentation allows the implantation process to occur when spacing is adequate, avoiding shadowing effects while still achieving high integration density in the final structure.
Solution Approach 2:
The patent performs preliminary actions by forming gate structures with increased spacing before the tilt-angle implantation process. The spacer layers are deposited and selectively removed to prepare the structure in advance, ensuring that when implantation occurs, the spacing is sufficient to prevent shadowing effects.
2Object-affected harmful factors
If the spacing between gate stacks is increased to reduce aspect ratio, then shadowing effects are mitigated, but device integration density decreases
Solution Approach 1:
The patent employs dynamic adjustment of gate structure dimensions through a multi-step process. The gate structures are temporarily formed with larger spacing for implantation, then spacer deposition and selective removal dynamically adjust the final spacing to the target dimension, optimizing both shadowing mitigation and integration density.
Solution Approach 2:
The patent changes the line width parameter of gate structures during fabrication. Initially, gate structures are formed at a narrower line width than the target width to increase spacing and reduce aspect ratio for better implantation. Subsequently, spacer processes adjust the parameter to achieve the final target width, balancing shadowing mitigation with integration density.
3Ease of manufacture
If polysilicon gate electrode is used in traditional designs, then fabrication process is simpler, but device performance decreases at smaller feature sizes
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal gate electrode. This material substitution improves device performance at smaller feature sizes by providing better electrical characteristics and control, while the overall fabrication process maintains simplicity through the use of standard deposition and etching techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves the formation of doped regions by reducing shadowing effects and maintaining device performance with reduced gate leakage, enabling efficient fabrication of integrated circuit devices at smaller technology nodes.
Implementation Method 1
high dielectric constant (high-k) gate insulator layers are also used, which allow greater physical thicknesses while maintaining the same effective thickness
Implementation Method 2
formation of pocket/lightly doped source/drain (LDD) regions by using tilt-angle implanting processes
Data Source
AI summary
A method for fabricating an integrated device is disclosed. A sacrificial gate stack is provided with a line width narrower than the target width of the final gate structure. After performing a tilt-angle implantation process, L-shape spacers are formed over the sidewalls of the sacrificial gate stack, and offset spacers are formed over the sidewalls of the L-shape spacers. An insulating layer is formed over the offset spacers and the substrate. Then, the sacrificial gate stack and the L-shape spacers are removed to form a trench in the insulating layer. A metal gate is then filled in the trench to form the final gate structure.