Gate Spacer Geometry for Short-Resistant Semiconductor Structures

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Solution Overview

Problem

The scaling down of semiconductor integrated circuits increases manufacturing complexity and the risk of electrical shorts between gate electrodes and source/drain regions due to the formation of corners during the fabrication process.

Innovation Solution

The formation of semiconductor device structures with gate spacers featuring straight portions and end portions at different angles, along with varying angles between these portions, reduces the risk of electrical shorts by enlarging the process window for removing sacrificial gate stacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but manufacturing complexity increases and the risk of electrical shorts increases

Engineering Contradiction:

Improveproduction efficiencyVSAvoidmanufacturing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The gate spacer is divided into a first portion and a second portion with different cross-sectional areas. This segmentation allows the structure to accommodate varying process conditions and reduces the risk of electrical shorts between the gate electrode and source/drain regions while maintaining scalability for high-density integration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the gate spacer are designed with different cross-sectional areas to serve different functions. The first portion has a larger cross-sectional area providing robust isolation, while the second portion has a smaller cross-sectional area reducing capacitance and interference. This local differentiation optimizes both reliability and performance in scaled devices.

Inventive Principle:

Principle #3Local quality

2Productivity

If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but the risk of electrical shorts between gate electrode and source/drain regions increases

Engineering Contradiction:

Improveproduction efficiencyVSAvoidrisk of electrical shorts

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gate spacer structure is designed with a first portion having a larger cross-sectional area that extends closer to the source/drain regions. This larger portion acts as a cushion or buffer zone that prevents electrical shorts before they can occur, providing inherent protection against process variations and dimensional control issues in scaled devices.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Ease of manufacture

If conventional gate spacer structure is used, then manufacturing process is simpler, but process window for removing sacrificial gate stacks is reduced

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidprocess window

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The gate spacer structure transitions from a uniform cross-section to a dynamic structure with varying cross-sectional areas along its length. This dynamic design provides an enlarged process window by accommodating variations in sacrificial gate stack removal processes, allowing for more flexible manufacturing conditions while maintaining precise dimensional control.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250113576A1Semiconductor device structure and methods of forming the same

Publication Date: 2025.04.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.