Gate Spacer Thickness Adjustment for MOS Strain Engineering
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Solution Overview
Problem
Current methods for enhancing carrier mobility in MOS devices, such as applying bi-axial in-plane tensile stress for NMOS and compressive stress for PMOS, face challenges in optimizing stress levels without increasing fabrication complexity, as NMOS devices require tensile CESLs and PMOS devices require compressive CESLs, affecting the inherent stresses applied to each.
Innovation Solution
The method involves forming gate spacers with adjustable thicknesses and etching specific portions to increase the strain in channel regions, allowing for tailored stress application through strained Contact Etch Stop Layers (CESLs) to enhance carrier mobility without adding complexity to the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tensile CESLs are formed on NMOS devices and compressive CESLs on PMOS devices to improve carrier mobility, then device performance is enhanced, but fabrication complexity increases due to requiring different stress types for different device types
Solution Approach 1:
The patent applies different gate spacer thicknesses to different device regions (NMOS vs PMOS) to achieve localized stress optimization. By making gate spacers in NMOS regions thinner than those in PMOS regions, the patent creates device-specific stress conditions without requiring separate CESL processing streams, thus maintaining fabrication simplicity while achieving local performance optimization
Solution Approach 2:
The patent changes the physical parameter of gate spacer thickness to control the type and magnitude of stress applied to underlying devices. By varying this geometric parameter, the patent achieves tensile stress in NMOS devices and compressive stress in PMOS devices, replacing the need for different CESL material compositions or deposition conditions
2Reliability
If gate spacer thickness is varied to adjust strain in channel regions, then carrier mobility is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning of gate spacers with different thicknesses before forming the CESL layer. By establishing the thickness differentiation early in the process flow, the patent ensures that subsequent CESL deposition and processing steps can proceed uniformly across all devices, reducing the cumulative precision requirements and allowing standard manufacturing tolerances to suffice
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively adjusts the strain in MOS devices, improving drive currents by varying the thickness differences of gate spacers, thereby optimizing the performance of both NMOS and PMOS devices without complicating the manufacturing process.
Implementation Method 1
forming a strained layer over the gate stack and the gate spacer... The strained layer includes a portion on an outer sidewall of the gate spacer and a portion over the gate stack
Data Source
AI summary
A method includes forming a gate stack over a semiconductor substrate, and forming a gate spacer on a sidewall of the gate stack. After the step of forming the gate spacer, the gate spacer is etched to reduce a thickness of the gate spacer. A strained layer is then formed. The strained layer includes a portion on an outer sidewall of the gate spacer, and a portion over the gate stack.