Gate Spacer Undercut Structure for Replacement Gate Formation
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Solution Overview
Problem
The shape of the gate spacer in semiconductor devices significantly influences the process of forming replacement gate electrodes, posing challenges in high integration technologies.
Innovation Solution
The semiconductor device incorporates a first gate spacer on the side surface of a first gate electrode extending into an undercut region and a second gate spacer on the side surface of a second gate electrode with varying horizontal widths, along with distinct gate dielectric layers to facilitate the formation of multiple active regions and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a gate spacer is formed on the side surface of a gate electrode in high integration semiconductor devices, then the replacement gate electrode formation process can be enabled, but the gate spacer shape becomes critical and difficult to control
Solution Approach 1:
The patent performs preliminary actions by forming mandrels with specific width variations before forming the gate spacers. The mandrels are designed with different widths in different regions, which pre-determines the gate spacer shape and width. This preliminary structuring enables precise gate spacer formation without requiring complex direct patterning, thus resolving the manufacturing precision challenge while maintaining replacement gate electrode formation capability.
Solution Approach 2:
The patent introduces mandrels as intermediary structures that mediate between the patterning process and the final gate spacer formation. These mandrels serve as temporary templates that define the gate spacer geometry, allowing indirect control of the gate spacer shape with high precision. The mandrels are later removed, having fulfilled their mediating role in transferring the desired geometry to the gate spacers.
2Productivity
If gate spacers with varying widths are formed to accommodate different active regions, then device integration is improved, but the process complexity increases
Solution Approach 1:
The patent segments the gate electrode structure into multiple parts by forming gate spacers with different widths corresponding to different active regions. Each gate spacer is tailored to its specific active region width, allowing independent optimization for each region. This segmentation enables high device integration with varying device dimensions without requiring a completely different process for each region, as the same mandrel-based approach is applied uniformly.
Solution Approach 2:
The patent utilizes parameter changes by varying the mandrel width parameter across different regions to achieve the desired gate spacer width variations. Instead of changing the fundamental process steps, the patent maintains process simplicity by only adjusting the mandrel dimensions parameter, which then automatically determines the appropriate gate spacer widths for different active regions, reducing overall process complexity.
3Manufacturing precision
If the gate spacer extends into the undercut region, then better control of gate electrode width is achieved, but the risk of damage to drain regions increases
Solution Approach 1:
The patent applies local quality by forming gate spacers with locally optimized widths that extend into the undercut region only where needed for precise gate electrode width control. The gate spacer width is tailored to match the local requirements of each active region, allowing extension into the undercut region for precision control while limiting the extent to prevent damage to adjacent drain regions. This localized optimization resolves the contradiction between precision control and damage prevention.
Data Source
AI summary
A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.