Gate Spacer Protection Layer for Overlay-Tolerant Via Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in protecting gate spacers during manufacturing processes, particularly during photolithography and etching, where overlay errors can lead to damage and degradation of the gate stack, causing shorting and reliability issues.
Innovation Solution
A method is introduced that involves forming a spacer protection layer over the gate spacers, which provides etch selectivity and protects the gate spacers during etching processes, ensuring the integrity of the gate stack and preventing shorting of source and drain vias with the gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If photolithography and etching processes are used for defining holes, then manufacturing efficiency is improved, but overlay errors cause gate spacer damage and device reliability deteriorates
Solution Approach 1:
A protection layer is formed over the gate spacer before the etching process to preemptively shield it from potential damage during subsequent manufacturing steps, allowing efficient processing without compromising device reliability
Solution Approach 2:
The protection layer acts as an intermediary between the etching process and the gate spacer, absorbing the harmful effects of overlay errors and preventing direct damage to the gate spacer while maintaining manufacturing efficiency
2Ease of manufacture
If etching processes are performed to create S/D and gate vias, then manufacturing progress is achieved, but gate spacer removal causes shorting and performance degradation
Solution Approach 1:
The protection layer is applied in advance to counteract the harmful effect of etching-induced gate spacer removal, enabling via formation while preventing shorting and maintaining gate stack performance
Solution Approach 2:
The protection layer converts the potentially harmful etching process into a beneficial operation by allowing aggressive etching parameters to be used for via formation while the protection layer absorbs any incidental damage that would otherwise affect the gate spacer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The spacer protection layer effectively prevents damage to the gate spacers during etching, maintaining the electrical performance and reliability of the semiconductor device, even in the presence of photolithography overlay errors, and can be integrated into existing IC fabrication flows.
Implementation Method 1
forming a spacer protection layer over the gate spacers, which provides etch selectivity and protects the gate spacers during etching processes
Data Source
AI summary
A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.