FinFET Gate Spacer Void Structure for Leakage and Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing parasitic capacitance and current leakage in FinFET devices due to the close proximity of gate structures to source and drain regions, which affects device performance and efficiency.
Innovation Solution
The introduction of air gaps between gate spacers and interlayer dielectric layers in the semiconductor structure, formed through a method involving the replacement of dummy gate structures with high-k metal gates and the removal of specific gate spacer portions, reduces parasitic capacitance and mitigates current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate structures are placed close to source and drain regions to reduce device footprint, then device density is improved, but parasitic capacitance and current leakage increase
Solution Approach 1:
An air gap is introduced as an intermediary element between the gate spacer and the interlayer dielectric layer. This air gap acts as a mediator that electrically isolates the gate structure from the source and drain regions, thereby reducing parasitic capacitance and current leakage while allowing the gate to remain in close proximity to the active regions for high device density.
Solution Approach 2:
The air gap is formed by removing a portion of the interlayer dielectric layer, effectively extracting material to create a void space. This extraction creates the necessary separation between conductive elements without increasing the overall device footprint, as the air gap occupies space that would otherwise be filled with dielectric material.
2Object-generated harmful factors
If air gaps are introduced between gate spacers and interlayer dielectric layers, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The air gap is formed as a preliminary feature during the interlayer dielectric formation process, before subsequent processing steps. By creating the air gap early in the fabrication sequence, the design is incorporated into the base structure, and later processing steps can proceed without additional complexity or specialized equipment.
Solution Approach 2:
The formation of the air gap involves changing the physical parameters of the interlayer dielectric layer by removing a portion of it. This parameter change (from solid dielectric to air-filled void) fundamentally alters the electrical characteristics between the gate spacer and underlying structures, reducing parasitic capacitance without requiring complex additional components.
Data Source
AI summary
A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.