Gate Spacer Projections for Void-Free FinFET Replacement Gates

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Solution Overview

Problem

As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, issues such as the formation of seams or voids during the filling of replacement gates in FinFETs become prevalent, affecting the performance and yield of the devices.

Innovation Solution

The formation of funnel-shaped gate electrodes in a replacement gate process for FinFETs is achieved by widening the recesses for the replacement gates through selective etching of gate spacers that have been modified by an impurity implantation, particularly using plasma oxidation to create oxidized regions in the spacers, which are then selectively etched to avoid seam formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but seams or voids form during replacement gate filling

Engineering Contradiction:
Improveintegration densityVSAvoidgate filling quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming projecting portions on the gate spacers before the replacement gate filling process. These projecting portions extend into the gate dielectric and create a physical barrier that prevents void formation during subsequent material deposition. By preparing the gate spacer structure in advance with these protrusions, the filling process can proceed without creating seams or voids, thus resolving the contradiction between high integration density and manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The projecting portions act as an intermediary structure between the gate spacer and the replacement gate material. These portions modify the geometry of the recess to be filled, creating a tapered or funnel-shaped configuration that facilitates complete material deposition without voids. The intermediary structure enables the filling process to succeed at reduced feature sizes where direct filling would otherwise fail.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the gate spacer is selectively etched to widen recesses for replacement gates, then funnel-shaped gate electrodes can be formed, but the gate spacer structure becomes more complex

Engineering Contradiction:
Improvegate electrode shape controlVSAvoidgate spacer structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating non-uniform structures on the gate spacer - specifically, projecting portions that extend into the gate dielectric at specific locations. These localized protrusions are formed through selective deposition or modification processes that affect only certain regions of the gate spacer. This local modification enables precise control over the recess geometry and subsequent gate electrode shaping without requiring complete structural redesign of the entire gate spacer.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the work function of the gate electrodes and reduces internal gate resistance, thereby improving the performance and yield of FinFETs by preventing voids during gate filling.

Implementation Method 1

plasma oxidation to create oxidized regions in the spacers

Methodology Applied
Scientific EffectPlasma oxidation: Oxidation

Data Source

PatentUS12444608B2Structure having gate spacers with projecting portions extending into a gate dielectric
Publication Date: 2025.10.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12444608B2 patent drawing
  • US12444608B2 patent drawing
  • US12444608B2 patent drawing

AI summary

In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.