Replacement Gate Structure With Laterally Etched Spacers for Low Capacitance
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Solution Overview
Problem
As semiconductor devices are scaled down, challenges arise in forming gate electrodes with reduced gate length, leading to increased gate capacitance and difficulties in metal filling, which can result in device performance issues and failure.
Innovation Solution
The formation of laterally etched spacers with varying widths, where the upper portion is wider and in contact with gate contacts, and the lower portion is narrower over the channel region, allows for improved metal filling uniformity and reduced gate capacitance by adjusting the gate electrode's dimensions during the replacement gate process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate electrode length is reduced to scale down semiconductor devices, then device density increases, but gate capacitance increases and metal filling becomes difficult
Solution Approach 1:
The gate electrode is segmented into two distinct portions: a first gate electrode portion and a second gate electrode portion. This segmentation allows each portion to have different lengths, enabling the first portion to maintain sufficient length for reliable metal filling while the second portion is reduced to achieve high device density. The segmentation resolves the contradiction by dividing the gate electrode into functional zones with different dimensional requirements.
Solution Approach 2:
Different portions of the gate electrode are assigned different local qualities in terms of dimensions. The first gate electrode portion has a longer length optimized for metal filling and electrical connection reliability, while the second gate electrode portion has a shorter length optimized for increasing device density. This local differentiation of quality allows simultaneous optimization of both contradictory requirements.
2Area of moving object
If gate electrode length is reduced uniformly, then device density increases, but device speed decreases due to increased gate capacitance
Solution Approach 1:
The gate electrode is divided into two portions with different lengths to simultaneously address device density and speed requirements. The first gate electrode portion maintains a longer length that reduces gate capacitance and improves device speed, while the second gate electrode portion is shorter to increase device density. This segmentation enables optimization of both speed and density without uniform reduction.
Solution Approach 2:
Different local regions of the gate electrode structure are assigned different dimensional qualities. The first portion retains longer dimensions favorable for low capacitance and high speed operation, while the second portion uses shorter dimensions for high density. This local quality differentiation resolves the contradiction between speed and density.
3Ease of manufacture
If spacer width is uniform, then manufacturing is simpler, but gate electrode dimensions cannot be optimized for both metal filling and capacitance reduction
Solution Approach 1:
The spacer structure is segmented into a first spacer portion and a second spacer portion with different widths. The first spacer portion has a wider width that enables better metal filling during electrode formation, while the second spacer portion has a narrower width that allows for reduced gate electrode length and lower capacitance. This segmentation of the spacer into different width zones enables optimization of gate electrode dimensions for both manufacturing and performance.
Solution Approach 2:
Different portions of the spacer are assigned different local widths to create varying constraints for gate electrode formation. The wider first spacer portion facilitates reliable metal filling, while the narrower second spacer portion enables capacitance reduction. This local quality variation in the spacer structure allows the gate electrode to achieve optimized dimensions for both ease of manufacture and device reliability.
Data Source
AI summary
The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.