Gate Stack Air Gap Structure Without Extra Lithography
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Solution Overview
Problem
Current methods for forming air gaps between stacked gate stacks in semiconductor devices struggle to achieve uniform height and shape with a large volume, often requiring additional photolithography processes, which increases complexity and costs.
Innovation Solution
A method involving the formation of a liner layer and dielectric stacks with different etching properties, allowing for the creation of air gaps without an additional photolithography process by using etching processes to control the height and shape of the air gaps between adjacent gate stacks, resulting in a uniform air gap with a larger volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an additional photolithography process is used to form air gaps, then the shape and height control of air gaps is improved, but the device complexity and fabrication cost increase
Solution Approach 1:
The patent extracts the air gap formation step from the conventional photolithography process by removing dielectric material between gate stacks through selective etching. This eliminates the need for additional photolithography steps while achieving controlled air gap formation, directly resolving the contradiction between precision and complexity.
Solution Approach 2:
The patent applies preliminary action by forming a sacrificial dielectric layer structure before the final air gap formation. The dielectric layers are deposited with specific thicknesses that enable subsequent selective removal to create uniformly spaced air gaps, achieving precision control without additional lithography.
2Reliability
If the air gap volume is increased to improve gate coupling rate, then the manufacturing precision of air gap dimensions becomes harder to control
Solution Approach 1:
The patent applies local quality by creating different dielectric layer thicknesses in different locations - thicker dielectric layers on gate stacks and thinner dielectric layers in gaps. This local variation enables selective etching that produces uniform air gaps with controlled dimensions and appropriate volume for gate coupling.
Solution Approach 2:
The patent changes physical parameters by controlling the thickness ratios of dielectric layers and selecting appropriate etching conditions. By adjusting these parameters, the air gap volume is optimized for gate coupling while maintaining uniform height and shape through the constrained etching geometry.
3Ease of manufacture
If conventional methods are used to form air gaps, then the fabrication cost increases due to additional photolithography, but the air gap volume is relatively small
Solution Approach 1:
The patent merges the air gap formation process with the existing dielectric layer deposition and etching processes. By combining multiple functions into the standard CMOS fabrication sequence without adding photolithography steps, the method reduces fabrication cost while achieving adequate air gap volume for improved gate coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process steps, saves fabrication costs, and enhances the reliability of semiconductor devices by achieving air gaps with consistent height and shape without the need for additional lithography, improving the control over air gap dimensions.
Implementation Method 1
performing an etching process without a patterned mask to remove the second dielectric layer and the first dielectric layer above the gap, and removing the first dielectric layer between the plurality of gate stacks to expose the liner layer
Data Source
AI summary
A semiconductor device with an air gap includes a plurality of gate stacks disposed on a substrate; a liner layer conformally covering the gate stacks and the substrate; and a dielectric stack disposed on the liner layer on the gate stacks. The air gap is formed between the liner layer and the dielectric stack on two adjacent gate stacks. A height of the air gap is greater than heights of the two adjacent gate stacks, and the air gap includes: a lower portion between the two adjacent gate stacks, sidewalls and a bottom of the lower portion exposing the liner layer; a middle portion above the lower portion; and an upper portion above the middle portion. Sidewalls of the upper portion expose the dielectric stack, a top surface of the upper portion is covered by the dielectric stack, and the upper portion has a smaller width than the lower portion.