Gate Stack Height Control via Bi-Layer Etch Stop
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, maintaining the height of gate stacks and spacers during manufacturing processes becomes increasingly challenging, leading to potential loss and reduced device performance.
Innovation Solution
A bi-layer film comprising a metal layer and a dielectric layer is formed over the gate stack and spacers, which are then patterned to serve as etch stop and planarization stop layers, allowing the height of the gate stack and spacers to be defined by a single etching step, thereby preventing loss during subsequent processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple planarization and etching steps are used to maintain gate stack and spacer height, then manufacturing precision may be improved, but device complexity and process time increase
Solution Approach 1:
The patent applies preliminary action by forming the bi-layer film structure (metal layer and dielectric layer) over the gate stack and spacers before subsequent etching and planarization steps. This pre-formed structure serves as a protective framework that defines the final height of gate stacks and spacers, preventing material loss during processing. The bi-layer film is deposited and patterned in advance to create etch stop and planarization stop layers, ensuring height consistency is built into the structure before final processing steps occur.
2Manufacturing precision
If multiple planarization and etching steps are performed, then height precision may be improved, but loss of gate stack and spacer material increases
Solution Approach 1:
The patent implements beforehand cushioning by depositing the bi-layer film structure (comprising a metal layer and a dielectric layer) over the gate stacks and spacers prior to etching and planarization steps. This bi-layer film acts as a protective cushion that prevents direct exposure of the gate stack and spacer materials to aggressive etching and planarization processes. The layered structure provides mechanical protection and chemical resistance, cushioning the underlying sensitive materials from damage and material loss during subsequent processing steps.
Solution Approach 2:
The bi-layer film structure serves as an intermediary between the processing tools and the gate stack/spacer materials. The metal layer and dielectric layer collectively function as a mediator that interfaces with etching and planarization processes, allowing these processes to proceed without directly contacting and damaging the gate stack and spacer materials. This intermediary structure enables precise height definition while protecting the underlying materials from loss.
3Manufacturing precision
If a bi-layer film structure is formed and patterned, then etch stop and planarization stop functionality is achieved, but device complexity increases
Solution Approach 1:
The bi-layer film structure performs multiple functions simultaneously: the metal layer provides etch stop functionality to prevent over-etching of underlying layers, while the dielectric layer provides planarization stop functionality to control the final surface height. This multi-functional design allows a single bi-layer structure to replace what would otherwise require separate etch stop and planarization stop layers, reducing overall structural complexity while maintaining precise height control capabilities.
Data Source
AI summary
In an embodiment, a method includes: forming a gate stack on a semiconductor fin, the gate stack having gate spacers along opposing sides of the gate stack; forming source/drain regions adjacent the gate stack; recessing the gate stack to form a first recess between the gate spacers; depositing a dielectric layer over the gate stack in the first recess; forming a first metal mask over the dielectric layer and the gate stack in the first recess; etching back the dielectric layer and the gate spacers to form a dielectric mask under the first metal mask; depositing a conductive material over the first metal mask and adjacent the gate stack; and planarizing the conductive material to form contacts electrically connected to the source/drain regions, top surfaces of the contacts and the dielectric mask being level.