Gate Stack Capping Layer Roughening for Leakage Reduction
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Solution Overview
Problem
The reduction in feature size of semiconductor devices leads to increased gate leakage current due to the reduced thickness of gate dielectric layers, posing challenges in the reliability and performance of high-performance semiconductor devices.
Innovation Solution
The semiconductor device incorporates a gate stack structure with a first capping layer having a roughened surface, formed through a wet-etching process, which enhances the formation of a second capping layer with a thicker bottom portion compared to its sidewall portion, improving the dielectric properties and reducing gate leakage current. This structure includes a dielectric layer made from high-k materials like hafnium oxide, with titanium nitride as the first capping layer and tantalum nitride as the second capping layer, and a gate electrode layer made from various metals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of gate dielectric layers is reduced to achieve smaller feature sizes, then the feature size is reduced, but the gate leakage current increases
Solution Approach 1:
The gate dielectric layer is segmented into multiple layers including a first capping layer, a gate dielectric layer, and a second capping layer. This segmentation allows each layer to have optimized thickness and material properties, enabling the overall structure to maintain low gate leakage current while supporting reduced feature sizes.
Solution Approach 2:
The gate stack uses composite materials with different properties - the first capping layer (e.g., titanium nitride), the gate dielectric layer (e.g., hafnium oxide), and the second capping layer (e.g., tantalum nitride). This composite structure combines the high-k properties of the dielectric layer with the protective and insulating properties of the capping layers, achieving both small feature size and low gate leakage.
2Productivity
If the gate dielectric layer thickness is reduced to improve device performance, then the device performance is improved, but the dielectric reliability deteriorates
Solution Approach 1:
The gate dielectric structure is divided into multiple functional layers that can be independently optimized. The gate dielectric layer provides high-k insulation for performance, while the first and second capping layers provide protective functions, allowing thin dielectric layers to be used without compromising reliability.
Solution Approach 2:
The first and second capping layers are deposited before and after the gate dielectric layer formation respectively, creating a protective cushion structure. This prevents damage to the thin dielectric layer during subsequent processing steps and provides additional insulation, cushioning against reliability issues that would otherwise result from reduced dielectric thickness.
3Ease of manufacture
If conventional processing methods are used for high-performance semiconductor devices, then the manufacturing process is simple, but the gate leakage current increases
Solution Approach 1:
The gate stack is manufactured as a segmented multi-layer structure using sequential deposition steps. Each layer (first capping layer, gate dielectric layer, second capping layer) is deposited in a separate step, allowing conventional processing equipment and methods to be used while achieving the complex structure needed to reduce gate leakage.
Solution Approach 2:
The invention uses composite material layers that can be deposited using conventional PVD, CVD, or ALD processes. By combining materials like titanium nitride, hafnium oxide, and tantalum nitride in a layered composite structure, the patent achieves reduced gate leakage without requiring non-conventional processing methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced dielectric properties of the gate stack significantly reduce gate leakage current, improving the reliability and performance of semiconductor devices by optimizing the thickness ratio of the capping layers and utilizing high-k dielectric materials.
Implementation Method 1
formed through a wet-etching process
Implementation Method 2
a dielectric layer made from high-k materials like hafnium oxide
Data Source
AI summary
A semiconductor device is provided including a substrate and a plurality of gate stacks. The gate stack includes a dielectric layer disposed on the substrate, a first capping layer disposed on the dielectric layer, a second capping layer disposed on the first capping layer, and a gate electrode layer covering the second capping layer. The first capping layer having a roughened surface may enhance the formation of the second capping layer. The second capping layer has a bottom portion and a sidewall portion, and the thickness of the bottom portion is formed to be greater than the thickness of the sidewall portion, so that the dielectric property of the second capping layer may be significantly improved. Further, a method for manufacturing the semiconductor device also provides herein.