Gate Stack Sidewall Dielectric Removal for Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in forming a gate stack for transistors is the difficulty in conformally depositing gate dielectric along the entire sidewalls of a recess, which can lead to increased parasitic capacitance, reduced inversion charge strength, and the risk of voids and imperfections, especially when replacing a placeholder gate with functional components.
Innovation Solution
A method is described where some or all of the gate dielectric is removed from the sidewalls of the recess, and a capping layer is formed on the gate dielectric within the recess, with the vertical portions of both being etched back to reduce parasitic capacitance and provide a wider recess for uniform gate metal deposition, improving the strength and uniformity of the inversion charge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate dielectric is conformally deposited along the entire sidewalls of the recess, then complete coverage is achieved, but parasitic capacitance increases and inversion charge strength decreases
Solution Approach 1:
The patent removes gate dielectric material from the sidewalls of the recess, extracting only the harmful portion while retaining the beneficial coverage. This selective removal reduces parasitic capacitance between the gate and source/drain regions while maintaining adequate gate dielectric coverage over the channel region.
Solution Approach 2:
The gate dielectric structure is made non-uniform, with different thicknesses or presence in different locations. The dielectric is present over the channel region for proper transistor operation but absent or reduced on the sidewalls to minimize parasitic effects, creating local variations in dielectric quality.
2Reliability
If gate dielectric is conformally deposited along the entire sidewalls of the recess, then complete coverage is achieved, but voids and imperfections occur
Solution Approach 1:
The patent removes gate dielectric material from the sidewalls of the recess, extracting only the harmful portion while retaining the beneficial coverage. This selective removal reduces parasitic capacitance while maintaining adequate gate dielectric coverage over the channel region.
Solution Approach 2:
Instead of attempting complete conformal coverage which causes deposition defects, the patent applies gate dielectric selectively - providing adequate coverage where needed (channel region) while omitting or reducing coverage where it causes problems (sidewalls), achieving partial action that avoids excessive action pitfalls.
3Adaptability or versatility
If placeholder gate is replaced with functional gate components, then device functionality is achieved, but parasitic capacitance and deposition issues arise
Solution Approach 1:
The patent removes gate dielectric material from the sidewalls of the recess, extracting only the harmful portion while retaining the beneficial coverage. This selective removal reduces parasitic capacitance while maintaining adequate gate dielectric coverage over the channel region.
Solution Approach 2:
The patent performs preliminary removal of sidewall gate dielectric before final gate metal deposition. This preliminary action prepares the structure by eliminating sources of parasitic capacitance and potential deposition defects, creating an optimized geometry for subsequent functional gate component formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, enhances switching speed and power efficiency, and improves the uniformity and reliability of the gate metal deposition, leading to better device performance.
Implementation Method 1
A chemical mechanical planarization process is performed on the workpiece to remove a portion of each of the barrier layer, the glue layer, and the electrode fill that extends beyond the gate recess
Implementation Method 2
A portion of each of the gate dielectric and the capping layer is removed from the vertical sidewall of each of the pair of opposing gate spacers
Data Source
AI summary
Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.