Gate Stack Dipole Tuning for Threshold Voltage Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor devices like MOSFETs, finFETs, and GAA FETs, which increases manufacturing complexity and makes it difficult to achieve lower and different threshold voltages for FETs, particularly for multi-functional low power portable devices.
Innovation Solution
The method involves forming NFETs and PFETs with similar work function metal layer thicknesses but different threshold voltages on the same substrate by using high-K gate dielectric layers doped with metallic dopants to induce dipoles of different polarities and concentrations, allowing for the adjustment of threshold voltages without varying the work function metal layer thicknesses, and incorporating a metallic oxide layer between the high-K gate dielectric and interfacial oxide layers to further tune the effective work function values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional gate structures are used with scaling down of semiconductor devices, then device dimensions are reduced, but manufacturing complexity increases and threshold voltage control becomes difficult
Solution Approach 1:
The patent changes the chemical composition parameter of the gate dielectric layer by doping it with metallic elements (such as aluminum, gallium, indium) to modify its electrical properties. This allows control of threshold voltage through compositional adjustment rather than structural complexity, resolving the contradiction between device scaling and manufacturing complexity.
Solution Approach 2:
The patent introduces a dipole layer as an intermediary between the gate dielectric layer and the channel region. This dipole layer, formed by metallic doping, mediates the electrical interaction and provides threshold voltage control without requiring complex multi-layer structures, thus simplifying manufacturing while enabling precise voltage control.
2Manufacturing precision
If work function metal layer thickness is varied to adjust threshold voltage, then different threshold voltages are achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
Instead of varying the thickness of work function metal layers (which requires precise thickness control and multiple deposition processes), the patent changes the doping concentration of metallic elements in the gate dielectric layer. This compositional parameter change achieves threshold voltage adjustment through a single material system, reducing manufacturing cost and process complexity.
Solution Approach 2:
The gate dielectric layer serves multiple functions: it provides electrical insulation, enables threshold voltage control through doping, and creates dipole effects. This multi-functionality eliminates the need for separate thick work function metal layers, simplifying the structure and reducing manufacturing steps while maintaining precise threshold voltage control.
3Adaptability or versatility
If multiple dopant types are used in gate dielectric layers, then different threshold voltages are achieved for NFET and PFET, but process complexity increases
Solution Approach 1:
The patent applies local quality by doping different regions (n-well and p-well) with appropriate metallic elements to create the required dipole moments for each transistor type. This localized doping approach enables independent threshold voltage control for NFET and PFET without requiring complex global processing changes.
Solution Approach 2:
The gate dielectric layer becomes a composite material containing the base dielectric (such as silicon oxide) plus metallic dopants (aluminum, gallium, indium). This composite structure provides both the insulating properties of the dielectric and the dipole-forming capability of the metals, enabling versatile threshold voltage control through material composition rather than process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by 20-30% and time by 15-20%, while enabling the creation of FET gate structures with smaller dimensions and lower threshold voltages, improving device performance and efficiency.
Implementation Method 1
forming a gate structure with a high-K gate dielectric layer doped with metallic dopants to induce dipoles of different polarities and concentrations
Implementation Method 2
incorporating a metallic oxide layer between the high-K gate dielectric and interfacial oxide layers to further tune the effective work function values
Data Source
AI summary
A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.