Gate Stack Divider Formation for SRAM Layout Density
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Solution Overview
Problem
As gate pitch shrinks, photolithography struggles to resolve 2-dimensional patterns, leading to undesired growth in end-to-end spacing between gate lines due to etching processes, which wastes space and affects layout density in high-density features like SRAM.
Innovation Solution
A method involving the formation of dummy gate stacks, gap-fill dielectric material, and printable dielectric dividers within trenches to define and maintain small end-to-end spacings, allowing for precise gate stack formation without increasing gap dimensions during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If photolithography is used to pattern gate lines at small pitch, then layout density is improved, but manufacturing precision deteriorates due to inability to resolve 2-dimensional patterns and etching erosion
Solution Approach 1:
The gate pattern is divided into multiple segments: continuous merged gate lines formed by first patterning step, and discrete gate stacks formed after removing dummy gate material and depositing gate stack material. This segmentation allows different regions to serve different functions - continuous lines for density and discrete stacks for precise spacing control.
Solution Approach 2:
Dummy gate stacks are formed in advance during the first patterning step, serving as placeholders that define the precise locations where gate stacks will eventually be formed. This preliminary action establishes the exact spacing before the actual gate material is deposited, preventing etching-induced spacing growth.
2Ease of manufacture
If etching processes are used to define gate patterns, then manufacturing capability is improved, but harmful factors increase due to erosion of short edges faster than long edges
Solution Approach 1:
Instead of directly etching the final gate pattern, the invention forms dummy gate stacks first, then removes them, and finally deposits gate stack material. This inverted approach allows the gate pattern to be defined by material deposition rather than etching, eliminating the edge erosion problem that plagues direct etching processes.
Solution Approach 2:
Dummy gate stacks serve as intermediary structures that facilitate the formation of the final gate pattern. They are formed first, used to define precise locations, then removed and replaced with actual gate stack material. This intermediary step protects against direct etching of the final pattern, preventing edge erosion.
3Area of stationary object
If gate pitch is reduced to increase layout density, then area utilization is improved, but measurement precision deteriorates due to photolithography resolution limits
Solution Approach 1:
The invention transitions from 2-dimensional photolithography patterning to a multi-step process involving dummy gate formation, dummy gate removal, and gate stack material deposition. This dimensional change in the manufacturing approach allows precise spacing control at small pitch that cannot be achieved with conventional 2-D photolithography alone.
Data Source
AI summary
A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.