Gate Stack Protection via Dual Spacer Encapsulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for fabricating semiconductor devices fail to adequately protect gate stacks comprising high-k dielectrics and metal gate-forming materials from subsequent wet etch chemistries, leading to exposure and potential catastrophic failure due to non-uniformities in the fabrication process, such as divots and footings, which create pathways for etchants to attack the gate stack-forming layers.
Innovation Solution
The implementation of a method involving the formation of two spacers around the gate stacks, where the first spacer is used as an etch mask to anisotropically etch exposed portions of the gate stack-forming layer, and a second spacer is formed adjacent to the first spacer to fully encapsulate the gate stack, preventing exposure to wet etch chemistries during subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single silicon nitride spacer is formed about sidewalls of the gate stack, then the gate stack is protected from wet etch chemistries, but non-uniformities in the fabrication process create divots and footings that expose portions of the gate stack-forming layer
Solution Approach 1:
The single spacer is divided into multiple spacers (first spacer, second spacer, and third spacer) formed at different stages. The first spacer is formed initially, then anisotropic etching removes exposed gate stack-forming layer, followed by formation of second and third spacers to achieve complete encapsulation. This segmentation overcomes the limitation of single-spacer non-uniformity by providing multiple protection layers.
Solution Approach 2:
The first spacer is formed preliminarily before complete encapsulation is achieved. This preliminary spacer provides initial protection during the anisotropic etching process, allowing subsequent spacers to be formed that complete the encapsulation. The preliminary action enables a staged approach to achieve uniform protection despite fabrication variations.
2Reliability
If the gate stack is fully encapsulated with multiple spacers, then complete protection from wet etch chemistries is achieved, but the fabrication process complexity increases
Solution Approach 1:
The gate stack and first spacer serve as a self-aligned etch mask during the anisotropic etching step. This self-service approach eliminates the need for separate mask formation steps, as the existing structures automatically define the etch pattern. The process uses the structures already present to protect themselves, reducing overall process complexity despite multiple spacer formations.
Solution Approach 2:
The first spacer is temporarily used during the anisotropic etching process as a protective mask, then selectively removed in subsequent steps. The second and third spacers are formed to provide the final encapsulation. This discarding and recovering approach allows the first spacer to serve its protective function temporarily without requiring permanent presence, enabling process optimization.
3Manufacturing precision
If anisotropic etching is used to remove exposed gate stack-forming layer, then the gate stack integrity is maintained, but the etching process requires precise control to avoid damaging protected regions
Solution Approach 1:
The gate stack and first spacer automatically form a self-aligned etch mask that defines the etch boundaries. This self-service mechanism ensures that the anisotropic etching removes only the exposed gate stack-forming layer while automatically protecting the regions covered by the spacer. The structures themselves provide the control needed for precise etching without requiring additional masking steps or complex process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects the gate stacks from wet etch chemistries, preventing void formation and ensuring the integrity of the semiconductor devices by completely encapsulating the high-k dielectrics and metal gate-forming materials, thus preventing catastrophic failure.
Implementation Method 1
The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask
Data Source
AI summary
Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.