Gate Stack Formation Without Dummy Gates
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Solution Overview
Problem
The semiconductor industry faces challenges in simplifying the manufacturing process of transistors, particularly in forming gate structures without the need for dummy gate structures, which complicates the process and increases costs.
Innovation Solution
The proposed solution involves depositing an interlayer dielectric directly on channel and source/drain regions of a substrate, etching openings to expose the channel regions, and then depositing layers of gate dielectrics and electrode materials to form gate stacks without preforming dummy gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy gate structures are formed before gate stacks, then gate structure formation is enabled, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the dummy gate structure formation step from the manufacturing process. By removing this unnecessary intermediate step, the process flow is simplified without compromising the ability to form gate stacks, directly addressing the contradiction between ease of manufacture and device complexity
Solution Approach 2:
The patent performs preliminary actions by forming the interlayer dielectric and sidewall spacers before gate stack deposition. This preliminary structuring enables direct gate stack formation without requiring dummy gates, reducing process complexity while maintaining manufacturing feasibility
2Manufacturing precision
If high aspect ratio dummy gates are patterned, then gate structure definition is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes the high aspect ratio dummy gate patterning step entirely. By extracting this complex and costly operation from the process, manufacturing cost is reduced while gate structure definition is maintained through alternative methods using the interlayer dielectric and sidewall spacer structure
Solution Approach 2:
The interlayer dielectric acts as an intermediary structure that enables gate definition without requiring dummy gates. This intermediate layer provides the necessary structural framework for precise gate stack formation at lower manufacturing cost
3Ease of operation
If dummy gate structures are formed, then gate structure formation is facilitated, but process flow is complicated
Solution Approach 1:
The patent inverts the conventional sequence by forming the interlayer dielectric and sidewall spacers before gate stack deposition, rather than using dummy gates first. This inverted approach simplifies the process flow while maintaining ease of gate structure formation through the alternative structural framework
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process flow, reduces processing complexity, and lowers manufacturing costs by eliminating the need to pattern high aspect ratio dummy gates, while also allowing for the formation of thin sidewall spacers that enhance the process window for forming gate stacks.
Implementation Method 1
depositing an interlayer dielectric directly on channel and source/drain regions of a substrate
Implementation Method 2
etching openings to expose the channel regions
Implementation Method 3
depositing layers of gate dielectrics and electrode materials to form gate stacks
Data Source
AI summary
A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.