Non-Planar Gate Stack Structure to Prevent Source/Drain Etch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit fabrication is the excessive source or drain etch during the dummy gate removal process, which leads to material loss and scaling issues, particularly as device dimensions approach the 10 nanometer node, where the constraints on lithographic processes become overwhelming and there is a trade-off between feature dimension and spacing.
Innovation Solution
The implementation of a process that mitigates source or drain etch by removing the thin oxide up to but not under the gate edge using a temporary spacer, eliminating the path for etch species and preventing material loss during dummy gate removal, and subsequent processes, such as channel shaping or nanowire release, by using a sacrificial or protective layer resistant to hydrofluoric acid etches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gate removal process is performed without protective measures, then gate structure can be removed, but source or drain material loss occurs due to excessive etch
Solution Approach 1:
A protective layer is introduced as an intermediary between the etch species and the source/drain material. This protective layer resists the hydrofluoric acid etch, preventing direct contact with the source/drain material while allowing the dummy gate removal process to proceed. The protective layer acts as a mediator that enables the removal process without causing material loss.
Solution Approach 2:
The protective layer is formed in advance before the dummy gate removal process. By preliminarily establishing this protective barrier, the source/drain material is pre-protected against the upcoming etch process. This preliminary action ensures that when the etch species are introduced, the source/drain material is already shielded and cannot be attacked.
2Productivity
If device dimensions are scaled down to 10 nanometer node, then increased device density is achieved, but lithographic process constraints become overwhelming
Solution Approach 1:
The solution moves the patterning challenge from the two-dimensional lithographic plane to the vertical dimension by using self-aligned processes. The protective layer and spacer structures are formed through vertical deposition and etching processes that automatically align with existing features, eliminating the need for additional lithographic steps at the 10 nanometer node and thereby reducing lithographic process constraints while maintaining high device density.
Data Source
AI summary
Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.