Gate Stack Etch Stop Layer Repair for Leakage Prevention
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Solution Overview
Problem
The existing etch stop layers in CMOS gate stack structures are ineffective in preventing over-etching, leading to damage of the barrier layer, which affects the performance, yield, and reliability of the final product.
Innovation Solution
A repair layer with similar material and electrical properties to the barrier layer is formed on the damaged surface, allowing for the increased formation speed and thickness of the etch stop layer within the gate stack structure's trench, thereby preventing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etch stop layer is formed to prevent over-etching the barrier layer, then the barrier layer protection is improved, but the formation speed and thickness of the etch stop layer are reduced
Solution Approach 1:
The patent divides the protective structure into multiple layers: a barrier layer and a separate etch stop layer formed thereon. This segmentation allows each layer to perform its specific function optimally - the barrier layer provides initial protection while the etch stop layer prevents over-etching, resolving the contradiction between protection effectiveness and formation speed by distributing the protective function across multiple specialized layers
Solution Approach 2:
The etch stop layer is formed preliminarily on the barrier layer before subsequent etching operations. This preliminary action ensures that the barrier layer is already protected with a sufficient thickness of etch stop material before the etching process begins, preventing over-etching while allowing the etch stop layer to be formed at optimized thickness to maintain formation speed
2Reliability
If the etch stop layer thickness is increased to improve coverage, then the current leakage prevention is improved, but the formation time is extended
Solution Approach 1:
The patent optimizes the thickness parameter of the etch stop layer to achieve sufficient current leakage prevention while minimizing formation time. By carefully controlling the thickness parameter within an optimal range, the patent resolves the contradiction between achieving adequate coverage for leakage prevention and maintaining efficient formation speed
Data Source
AI summary
A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.