Peripheral Gate Work Function Stack With Graphene Liner
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in the design of gate structures where existing technologies struggle to maintain low resistance and efficient performance.
Innovation Solution
A semiconductor device design featuring a peripheral gate structure with a U-shaped cross-sectional profile, incorporating a peripheral work function layer made of titanium, titanium nitride, silicon, or silicon germanium, a graphene first peripheral liner layer, and a tungsten or tungsten nitride first peripheral interconnect layer, which improves the low resistance and performance of the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to meet increasing computing demand, then device density and computing ability are improved, but quality, yield, performance, and reliability deteriorate
Solution Approach 1:
The patent applies different material compositions and structural configurations to different regions of the gate structure. The work function layer uses specific materials (titanium, titanium nitride, silicon, or silicon germanium) with controlled thicknesses to achieve optimal electrical characteristics locally, while the interconnect layer uses tungsten or tungsten nitride with graphene liner to reduce resistance. This localized optimization allows the device to maintain high performance and reliability even as overall dimensions are scaled down.
2Reliability
If the peripheral gate structure width is increased to improve performance, then device performance is enhanced, but device complexity increases
Solution Approach 1:
The peripheral gate structure is divided into distinct functional layers: a work function layer (titanium, titanium nitride, silicon, or silicon germanium) for electrical characteristic control, an interconnect layer (tungsten or tungsten nitride) for current conduction, and a graphene liner layer for interface protection. This segmentation allows each layer to be independently optimized and manufactured, reducing overall process complexity while achieving superior performance.
Solution Approach 2:
The patent employs composite material structures where multiple materials are stacked in specific sequences. The work function layer combines different materials with complementary properties to achieve desired work function values, while the interconnect layer combines tungsten (or tungsten nitride) with graphene to simultaneously achieve low resistance and good interface quality. These composite structures enhance performance without proportionally increasing complexity.
Data Source
AI summary
The present application discloses a semiconductor device. The semiconductor device includes a substrate; a peripheral gate structure including: a peripheral gate insulating layer inwardly positioned in the substrate and including a U-shaped cross-sectional profile, a peripheral work function layer positioned on the peripheral gate insulating layer and including a recess, a first peripheral interconnect layer positioned on the peripheral work function layer, a first peripheral liner layer positioned between the peripheral work function layer and the first peripheral interconnect layer, and a peripheral capping layer positioned on the first peripheral interconnect layer. The peripheral work function layer includes titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. The first peripheral liner layer includes graphene. The first peripheral interconnect layer includes tungsten, tungsten nitride, or a combination thereof.