Gate Stack Height Variance Reduction via Liner Layer Compensation
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Solution Overview
Problem
Semiconductor devices like FETs often experience gate stack height variances due to uneven dummy gate removal, leading to performance issues unless corrected.
Innovation Solution
A method involving the removal of hard mask layers and spacers, followed by the deposition of a liner layer and inter-layer dielectric over dummy gates, with subsequent partial removal of the liner layer and eventual removal of the dummy gates to reduce height variance between gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy gates are formed and various layers (hard mask, spacers) are formed over/around them during fabrication, then device formation can proceed through standard stages, but gate stack height variance occurs among the gate stacks which propagates through subsequent stages leading to performance issues
Solution Approach 1:
The patent applies preliminary action by forming a liner layer over the dummy gates before forming the inter-layer dielectric. This liner layer is then selectively removed to compensate for height variances. The preliminary formation of this compensation structure allows subsequent layers to be deposited at a uniform height, preventing the propagation of height variance through later fabrication stages while maintaining standard manufacturing processes.
2Productivity
If dummy gates are removed unevenly, then gate stack height variance occurs, but complete removal is difficult to achieve uniformly across all gate stacks
Solution Approach 1:
The patent uses an intermediary approach by introducing a liner layer that remains after dummy gate removal. This liner layer acts as a mediator that compensates for the uneven removal of dummy gates. Instead of requiring perfectly uniform dummy gate removal, the liner layer provides the necessary height compensation, allowing non-uniform removal while still achieving uniform final gate stack heights.
3Reliability
If spacer heights are uneven due to previous height variance, then device performance deteriorates, but correcting this requires additional process steps
Solution Approach 1:
The patent applies preliminary action by forming the liner layer and inter-layer dielectric before the spacer formation process. This preliminary height compensation ensures that when spacers are subsequently formed, they deposit on a uniform surface, resulting in uniform spacer heights. This approach corrects potential performance issues before they manifest, avoiding the need for additional corrective process steps later.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate stack height variance, improving the uniformity and performance of semiconductor devices by eliminating height disparities between gate stacks.
Implementation Method 1
depositing a liner layer and an inter-layer dielectric (ILD) over the set of dummy gates
Implementation Method 2
depositing a liner layer and an inter-layer dielectric (ILD) over the set of dummy gates
Data Source
AI summary
In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.