Gate Stack Integration for Non-Volatile Memory and CMOS
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Solution Overview
Problem
The integration of non-volatile memory cells into standard CMOS process flows is challenging due to differing material requirements and process conditions between memory cells and CMOS circuitry, necessitating a unified integration scheme that can accommodate various memory cell types without significant modifications to photolithographic masks.
Innovation Solution
A method involving the simultaneous patterning and processing of gate stacks in memory and peripheral areas, where a first gate stack for CMOS circuitry and a second gate stack for memory cells are patterned and filled with insulating or conductive materials, allowing for shared etch processes and reduced topology in the transition area to facilitate integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-volatile memory cells with materials like alumina or tantalum nitride are integrated into standard CMOS process flows, then memory functionality is achieved, but process compatibility and manufacturing complexity deteriorate due to differing material requirements between memory cells and CMOS circuitry
Solution Approach 1:
The patent divides the integrated circuit into distinct memory areas and peripheral areas, allowing different material systems to be used in each region. The memory area can utilize non-volatile memory materials (alumina, tantalum nitride) while the peripheral area uses standard CMOS materials, with each area processed independently through area-selective etching and filling operations
Solution Approach 2:
The patent introduces intermediate structures including transition areas with dummy gate lines, etch stop layers, and fill materials that mediate between the memory area and peripheral area. These intermediary elements enable process compatibility by providing transition zones where different material systems can coexist and be processed through shared etch and fill operations
2Adaptability or versatility
If different memory cell types (TANOS, SONOS) are integrated, then memory cell versatility is improved, but photolithographic mask modifications and process adaptability worsen
Solution Approach 1:
The patent creates a universal integration platform where a single photolithographic mask set can pattern both memory area structures and peripheral circuit structures. The shared etch processes and unified gap filling operations allow the same mask patterns to define features for different memory cell types (TANOS, SONOS) and CMOS circuitry simultaneously, eliminating the need for mask modifications when switching between memory cell types
3Manufacturing precision
If separate processing is used for memory cells and CMOS circuitry, then manufacturing precision is maintained, but productivity and integration efficiency deteriorate
Solution Approach 1:
The patent merges previously separate processing sequences into unified operations. Shared etch processes simultaneously pattern both memory area and peripheral area structures using area-selective etching. Unified gap filling operations deposit insulator or conductor materials across the entire wafer, filling gaps in both memory and peripheral areas in a single process step, thereby maintaining precision while doubling productivity
Data Source
AI summary
An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.