CMOS Gate Stack Isolation for Reliable GAA Transistor Scaling
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, which affects the reliability and efficiency of semiconductor integrated circuits.
Innovation Solution
The solution involves forming nanostructure transistors with gate all around (GAA) structures using sacrificial nanostructures and channel nanostructures made of different materials, with a gate stack structure wrapped around the nanostructure stacks, and employing advanced processes like molecular beam epitaxy and metal-organic chemical vapor deposition for epitaxial growth, along with spacer layers and inner spacer layers to create reliable transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The gate stack structure is wrapped around the nanostructure stacks in a nested configuration, with the gate dielectric layer and gate electrode layer surrounding the channel nanostructures. This three-dimensional gate-all-around structure provides superior electrostatic control while enabling continued scaling to smaller feature sizes without proportionally increasing process complexity
Solution Approach 2:
The device structure is segmented into distinct functional regions including sacrificial nanostructures, channel nanostructures, gate dielectric layers, and gate electrode layers. This segmentation allows each component to be optimized and formed using specialized processes, improving overall device performance while managing fabrication complexity through modular construction
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but device reliability deteriorates
Solution Approach 1:
The gate stack completely surrounds the channel nanostructures in a nested configuration, providing 360-degree electrostatic control. This gate-all-around structure maintains excellent electrical performance and device reliability even as feature sizes decrease, because the gate controls the channel from all directions, compensating for the reduced dimensions
Solution Approach 2:
The device employs composite material structures including alternating layers of semiconductor materials (e.g., Si/SiGe) for the channel and sacrificial regions, with high-k gate dielectric materials and metal gate electrodes. These composite structures provide superior electrical characteristics and reliability while enabling continued scaling to smaller feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and efficiency of semiconductor devices by improving the scaling of semiconductor device structures, reducing process-induced interferences, and increasing the yield of CMOS devices, allowing for smaller feature sizes while maintaining device performance.
Implementation Method 1
employing advanced processes like molecular beam epitaxy and metal-organic chemical vapor deposition for epitaxial growth
Implementation Method 2
employing advanced processes like molecular beam epitaxy and metal-organic chemical vapor deposition for epitaxial growth
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate, an isolation layer, a gate stack structure, and a dielectric layer. The method includes partially removing the gate stack structure to form a first trench in the gate stack structure. The method includes forming an isolation structure in the first trench. The method includes removing the first gate stack and the second gate stack to form a first recess and a second recess in the dielectric layer. The method includes forming an n-type gate stack and a p-type gate stack in the first recess and the second recess respectively. The method includes forming a conductive line over the n-type gate stack, the p-type gate stack, and the isolation structure. The conductive line electrically connects the n-type gate stack to the p-type gate stack.