Gate Stack Electrode Segmentation for Low-Leakage Semiconductor Memory
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Solution Overview
Problem
Semiconductor devices face issues with process failure and increased leakage current due to contamination, which affect their operating characteristics and data storage capacity.
Innovation Solution
The semiconductor device incorporates a design with gate stack structures, separation structures, and vertical structures that include electrodes, cell dielectric layers, barrier layers, separation dielectric patterns, and capping patterns to reduce contamination and improve operating characteristics by separating upper electrodes and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate stack structures are used to increase data storage capacity, then data storage capacity is improved, but process failure and leakage current increase due to contamination
Solution Approach 1:
The patent divides the gate electrode into multiple segments separated by separation dielectric patterns. This segmentation isolates different regions of the gate structure, preventing contamination from spreading between segments and reducing leakage current while maintaining the overall data storage capacity of the device.
Solution Approach 2:
The patent introduces separation dielectric patterns and capping patterns as intermediary structures between the gate electrodes and surrounding environment. These intermediary layers act as barriers that prevent contamination from reaching critical interfaces, thereby reducing process failure and leakage current without compromising storage capacity.
2Reliability
If separation structures are introduced to reduce leakage current, then operating characteristics are improved, but device complexity increases
Solution Approach 1:
The patent employs thin film separation dielectric patterns and capping patterns that conformally cover the gate structures. These thin film structures provide effective isolation against leakage current while occupying minimal space and adding relatively little structural complexity compared to bulk separation structures.
Solution Approach 2:
The patent addresses leakage current by introducing separation structures in the vertical dimension (through the thickness of the gate stack) rather than only in the horizontal plane. The separation dielectric patterns extend through the gate electrode thickness, providing effective isolation without significantly increasing the lateral footprint of the device.
Data Source
AI summary
Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.