Work-Function Metal Gate Stack for Memory Uniformity and Logic Drive
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Solution Overview
Problem
The challenge lies in forming gate electrodes for semiconductor devices that simultaneously achieve uniform electrical characteristics in memory cell areas and high current driving capability in logic areas, while simplifying the fabrication process.
Innovation Solution
The semiconductor device incorporates a substrate with distinct active areas for memory and logic regions, featuring gate electrodes with specific metal layer configurations, including work-function metal layers, capping layers, N-work-function metal layers, barrier metal layers, and conductive layers, tailored to meet the electrical requirements of each area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes with different configurations are formed in memory cell areas and logic areas, then uniform electrical characteristics in memory areas and high current driving capability in logic areas can be achieved, but the fabrication process complexity increases
Solution Approach 1:
The gate electrode structure is segmented into different configurations for memory cell areas and logic areas. Memory area gate electrodes include both first and second conductive layers with specific work-function metal layers, while logic area gate electrodes include only the first conductive layer with different work-function metal layer configurations, allowing area-specific electrical characteristics without requiring completely separate fabrication processes
Solution Approach 2:
Different work-function metal layer configurations are applied locally to different areas: memory cell areas receive both P-type and N-type work-function metal layers for uniform electrical characteristics, while logic areas receive only P-type or only N-type work-function metal layers for high current driving capability, achieving area-optimized performance within a unified process framework
2Productivity
If gate electrode widths are decreased for high integration, then device density increases, but maintaining uniform electrical characteristics and high current capability across different areas becomes more difficult
Solution Approach 1:
Even with decreased gate electrode widths for high integration, the patent applies local quality by configuring memory area gate electrodes with both first and second conductive layers and specific work-function metal layers to maintain uniform electrical characteristics, while logic area gate electrodes use different configurations to preserve high current driving capability, achieving area-specific optimization despite overall size reduction
Data Source
AI summary
In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.