Gate Stack Integrated Metal Resistors for Scaling
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Solution Overview
Problem
Conventional methods for forming metal resistors in MOSFETs face scaling issues at reduced scales, leading to complexity in subsequent patterning and etching processes due to topography-related problems.
Innovation Solution
Integrating metal resistors into the gate stack structure, which involves forming a gate stack with a self-aligning cap and gate metal, patterning a resist mask to expose the gate stack, removing the cap and metal, and depositing a resistor metal within the gate stack, followed by forming bar contacts and contact vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form planar metal resistors with middle of line processes, then metal resistors can be formed, but topography complexity arises that causes difficulty for subsequent patterning and etching processes at reduced scale
Solution Approach 1:
The patent merges the metal resistor formation process with the gate stack formation process by integrating the resistor metal layer deposition into the gate stack fabrication sequence. This consolidation eliminates the need for separate middle of line processes, thereby reducing topography complexity while maintaining manufacturing precision for metal resistors at reduced scales
Solution Approach 2:
The patent performs preliminary actions by forming the resistor metal layer during the gate stack fabrication process before subsequent patterning and etching steps. This preliminary integration of resistor formation prevents topography issues from arising later in the process, simplifying subsequent manufacturing steps
2Ease of manufacture
If metal resistors are formed using middle of line processes, then resistors can be created, but subsequent patterning and etching processes become complex at reduced scale
Solution Approach 1:
The patent combines multiple manufacturing operations into a unified process sequence where metal resistor formation is integrated with gate stack fabrication. This merging eliminates the need for complex middle of line processes and simplifies subsequent patterning and etching steps by reducing topography variability
Solution Approach 2:
The gate stack fabrication process is made multi-functional by simultaneously forming both the gate structure and the metal resistor. This universal approach allows a single process sequence to accomplish multiple objectives, thereby simplifying subsequent manufacturing steps while maintaining ease of resistor creation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach addresses scaling issues and simplifies the patterning process by integrating metal resistors into the gate stack, improving the scalability and reducing complexity in subsequent processing steps.
Implementation Method 1
depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed
Implementation Method 2
depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack
Data Source
AI summary
Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.