High-Aspect-Ratio Gate Stack Notch Profile Against Collapse
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down gate structures with high aspect ratios, as they are prone to collapse during fabrication and can result in residue issues that affect device uniformity and performance, particularly in advanced process nodes where channel lengths and critical dimensions decrease, leading to metal gate protrusion and shorting problems.
Innovation Solution
A method for forming gate stacks with a high aspect ratio that includes creating a notch in the footprint profile of the gate structure to enhance mechanical strength and reduce the risk of metal gate protrusion, involving a series of fabrication steps including forming mandrel patterns, sacrificial layers, and replacing dummy gates with high-k metal gate stacks, which inherit the notch profile to prevent shorting and maintain device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate structures are scaled down with decreasing critical dimensions, then production efficiency increases and costs decrease, but gate aspect ratio increases leading to collapse and residue issues
Solution Approach 1:
The gate structure is segmented into multiple functional layers including a first gate electrode, a second gate electrode, and an interlayer dielectric. This segmentation allows each layer to be optimized independently, reducing the aspect ratio of individual structures while maintaining the overall gate functionality, thereby preventing collapse during fabrication
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional stacked gate structure with multiple electrodes arranged vertically. This dimensional change allows the gate to maintain effective control over the channel while reducing the lateral footprint and aspect ratio of individual gate components
2Length of moving object
If gate critical dimensions are decreased, then device scaling is achieved, but residue remains in intersecting junctions causing uniformity issues and performance deterioration
Solution Approach 1:
The mandrel structure is formed preliminarily to define the gate pattern before the actual gate electrodes are deposited. This preliminary structure serves as a template that ensures precise pattern transfer and eliminates residue in intersecting junctions, maintaining manufacturing precision even as critical dimensions decrease
Solution Approach 2:
The interlayer dielectric acts as an intermediary between the first and second gate electrodes, providing mechanical support and electrical isolation. This intermediary layer prevents residue accumulation at junctions and ensures uniform gate structure formation during the patterning process
3Ease of manufacture
If high aspect ratio dummy gate is used, then gate-last process is enabled, but gate collapse occurs during fabrication
Solution Approach 1:
The gate structure uses composite materials with different mechanical and electrical properties. The first gate electrode uses a material optimized for mechanical strength to prevent collapse, while the second gate electrode uses a material optimized for electrical performance, allowing the gate-last process to proceed without collapse
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, an isolation feature over the semiconductor substrate, a fin protruding from the semiconductor substrate and through the isolation feature, a gate stack over and engaging the fin, and a gate spacer on sidewalls of the gate stack. A bottom portion of the sidewalls of the gate stack tilts inwardly towards the gate stack.