Integrated Circuit Gate Stack Structures with Varying Oxide Treatments
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Solution Overview
Problem
Conventional methods for fabricating integrated circuits with both p+ and n+ gate electrodes face challenges in maintaining dopant type integrity, particularly with p-type dopants diffusing through gate oxides, leading to poor electrostatic gate control and increased noise in analog circuitry, especially in image sensors.
Innovation Solution
The method involves forming gate stack structures with varying oxide layer thicknesses and nitrogen concentrations, along with conductive layers of differing conductivity types and active dopant concentrations, to create both p-type and n-type gate electrodes suitable for high-speed digital and analog processing without increased noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nitrided gate oxide is used to prevent p-type dopant diffusion, then dopant type integrity is improved, but noise in analog circuitry increases
Solution Approach 1:
The patent applies different gate oxide treatments to different device regions: nitrided gate oxide is used for digital devices requiring dopant protection, while non-nitrided gate oxide is used for analog devices where noise must be minimized. This local differentiation resolves the contradiction by allowing each region to have the properties it needs without compromising the other.
Solution Approach 2:
The patent segments the integrated circuit into digital and analog regions with distinct gate oxide characteristics. By dividing the circuit into separate zones with different oxide treatments, the patent enables dopant protection in digital areas while maintaining low noise performance in analog areas, thus resolving the fundamental contradiction between these two requirements.
2Manufacturing precision
If p-type implant is used to create buried junction for n+ gate electrodes in PMOS devices, then threshold voltage control is improved, but electrostatic gate control deteriorates
Solution Approach 1:
Instead of using a buried junction (p-type implant) to control threshold voltage, the patent inverts the approach by using a lightly-doped extension region that extends under the gate. This inverted structure maintains direct gate control over the channel while still enabling threshold voltage adjustment, thus resolving the contradiction between threshold voltage control and electrostatic gate control.
Solution Approach 2:
The patent changes the doping parameters in the extension region, using light doping concentrations that allow the gate to maintain electrostatic control while still providing the necessary threshold voltage adjustment. By carefully controlling the dopant concentration and distribution in the extension region, the patent achieves both objectives without the need for a buried junction.
3Ease of manufacture
If n+ polysilicon gate electrodes are used throughout the integrated circuit, then manufacturing cost is reduced, but device performance for both digital and analog circuits deteriorates
Solution Approach 1:
The patent uses different gate electrode doping types in different circuit regions: n+ polysilicon gates for digital devices and p+ polysilicon gates for analog devices. This local differentiation allows each device type to have optimal performance characteristics while still using polysilicon gates throughout, thus resolving the contradiction between manufacturing simplicity and device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of integrated circuits with p and n-type gates, achieving different threshold voltages and reducing noise, particularly in image sensors, by controlling dopant diffusion and improving electrostatic gate control, thus enhancing the performance of both digital and analog circuitry.
Implementation Method 1
One of the biggest challenges in the process flow used to fabricate both p+ and n+ gate electrodes is to keep the dopant types, particularly p-type dopants, such as boron, from diffusing through the gate oxide into the channel regions of the devices during the thermal processing steps.
Implementation Method 2
A nitridation process is conducted to form a first nitrided oxide layer from at least a portion of the first oxide layer.
Data Source
AI summary
A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and nitrogen concentrations and gate electrodes with differing conductivity types and active dopant concentrations.