Gate Stack with Oxygen Scavenging Layer for pVt Stability
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Solution Overview
Problem
The stability and control of threshold voltage (Vt) in pFET devices become challenging due to the response of oxygen vacancies in high-k dielectric materials during the replacement metal gate fabrication process, especially when using untreated TiN or TaN as work function metals, leading to unstable pVt and difficulty in achieving desired performance in nFET devices.
Innovation Solution
A gate stack with a weak oxygen-scavenge stack is formed, incorporating a barrier layer like TiN or TaN and a strong oxygen-scavenge material such as TiAlC, TiAl, Al, or NbAlC, to define and adjust the pVt, which is more stable and reliable compared to single metal nitride layers like TiN and TaN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If untreated TiN or TaN is used as work function metals in pFET devices, then the fabrication process is simple, but the threshold voltage becomes unstable due to oxygen vacancies in high-k dielectric materials
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a high-k dielectric layer, an oxygen-scavenging layer (TiAlC, TiAl, Al, or NbAlC), and a metal nitride layer (TiN or TaN). This segmentation allows each layer to perform its specific function - the oxygen-scavenging layer absorbs oxygen vacancies while the metal nitride provides work function, collectively stabilizing threshold voltage without requiring complex additional structures
Solution Approach 2:
The patent employs composite material structures combining high-k dielectric materials with oxygen-scavenging materials (TiAlC, TiAl, Al, NbAlC) and metal nitrides (TiN, TaN). This composite approach creates a gate stack where materials work synergistically - the oxygen-scavenging layer compensates for oxygen vacancies in the high-k dielectric while maintaining electrical performance, achieving stable pVt without overly complicating the overall structure
2Manufacturing precision
If a single metal nitride layer like TiN or TaN is used, then the device structure is simple, but it is difficult to achieve desired performance in nFET devices due to Vt variation
Solution Approach 1:
The gate stack is divided into distinct functional segments: the high-k dielectric layer, the oxygen-scavenging layer (TiAlC, TiAl, Al, or NbAlC), and the metal nitride layer. This segmentation enables precise control of threshold voltage by independently optimizing each layer's properties - the oxygen-scavenging layer thickness and composition can be tuned to achieve desired Vt control while maintaining structural simplicity
Solution Approach 2:
The patent utilizes parameter changes in the oxygen-scavenging layer composition (TiAlC, TiAl, Al, NbAlC) and thickness to precisely control threshold voltage. By adjusting the oxygen-scavenging capability parameters of this intermediate layer, the gate stack achieves desired Vt control for nFET devices while keeping the overall structure relatively simple through systematic material parameter optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The weak oxygen-scavenge stack effectively stabilizes the pVt and improves the performance and reliability of nFET devices by reducing Vt variation, enhancing the overall stability and control of the gate stack in MOSFET devices.
Implementation Method 1
depositing a scavenging layer on the first nitride layer... a weak oxygen-scavenge stack is formed, incorporating a barrier layer like TiN or TaN and a strong oxygen-scavenge material such as TiAlC, TiAl, Al, or NbAlC
Data Source
AI summary
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.