3D Gate Stack Memory Layout With Pass Gate Area Reduction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density while maintaining effective data storage and retrieval operations.
Innovation Solution
The semiconductor memory device incorporates a gate stack with conductive patterns stacked in a specific direction, a pass gate overlapping the contact region, a doped semiconductor layer overlapping the cell array region, and active pillars passing through the pass gate, enhancing integration density and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory device structures are used, then manufacturing and operation are simpler, but integration density cannot be increased effectively
Solution Approach 1:
The patent implements a three-dimensional stacked architecture where memory cells are arranged vertically across multiple layers rather than in a planar two-dimensional layout. Conductive patterns are stacked in the first direction (vertical) while extending in the second direction (horizontal), creating a multi-layered structure that significantly increases integration density by utilizing the third dimension (height) for component placement.
Solution Approach 2:
The patent employs nested structures where channel pillars are positioned within cell array regions defined by gate stacks, and active pillars are integrated within pass gate structures. The pass gate overlaps the contact region while the doped semiconductor layer overlaps the cell array region, creating overlapping and nested spatial arrangements that maximize space utilization and increase integration density without proportionally increasing overall device footprint.
2Quantity of substance
If pass circuit area is reduced to increase integration density, then more memory cells can be packed, but connectivity and data retrieval operations may be compromised
Solution Approach 1:
The pass gate is positioned to overlap the contact region in the vertical direction, creating a three-dimensional arrangement where the pass gate extends in the first direction (vertical stacking) while the contact region lies in the second direction (horizontal plane). This vertical stacking allows the pass circuit to control multiple memory cell strings simultaneously, reducing the horizontal area required for pass circuits while maintaining their connectivity function through the vertical dimension.
Solution Approach 2:
The pass gate structure serves multiple functions: it acts as a control gate for the pass transistor, provides electrical connection through the contact region, and enables data retrieval operations for multiple memory cell strings simultaneously. The doped semiconductor layer also serves dual purposes as both a semiconductor region for transistor formation and a connection pathway, reducing the need for separate dedicated structures and maintaining reliability while reducing area.
Data Source
AI summary
A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stack, a pass gate overlapping a contact region of the gate stack and opening a cell array region of the gate stack, a doped semiconductor layer spaced apart from the pass gate and overlapping the cell array region of the gate stack, and an active pillar passing through the pass gate.