Gate Stack Passivation for SiGe FinFET Defect Reduction

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Solution Overview

Problem

As semiconductor devices approach smaller feature sizes, such as 5 nm or 3 nm technology nodes, they face challenges with interfacial and charge defects (Dit) that degrade performance, particularly when using materials like epitaxially grown silicon germanium, which boosts carrier mobility but introduces defects.

Innovation Solution

The process involves forming semiconductor fins with isolation regions, a dummy gate dielectric and electrode, and a passivation process using fluorine to reduce dangling bonds and defects in the n-metal work function layer, thereby minimizing aluminum diffusion and enhancing device performance without increasing thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If epitaxially grown silicon germanium is used to boost carrier mobility, then device performance is improved, but interfacial and charge defects increase

Engineering Contradiction:
Improvedevice performanceVSAvoidinterfacial and charge defects
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A passivation layer is introduced as an intermediary between the silicon germanium fin and the n-metal work function layer. This passivation layer mediates the interface by reducing dangling bonds and preventing direct contact between defective surfaces, thereby reducing interfacial defects while preserving the high carrier mobility benefit of silicon germanium

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the chemical and physical parameters of the interface by applying a passivation treatment that modifies surface properties. This reduces the density of interface states and charge defects without altering the bulk properties of the silicon germanium that provide high carrier mobility

Inventive Principle:
Principle #35Parameter changes

2Productivity

If feature size is reduced to increase integration density, then more components are integrated into a given area, but manufacturing precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidminimum feature size control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The dummy gate dielectric and electrode are formed in advance before the actual gate structure is created. This preliminary action establishes a reference framework that guides subsequent patterning steps, enabling precise formation of smaller features while maintaining manufacturing control

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate structure is divided into multiple components (dummy gate dielectric, dummy gate electrode, actual gate dielectric, actual gate electrode) formed in separate sequential steps. This segmentation allows each component to be optimized and controlled independently, facilitating precise manufacturing at smaller feature sizes

Inventive Principle:
Principle #1Segmentation

3Object-generated harmful factors

If a passivation process is applied to reduce defects, then interfacial and charge defects are reduced, but process complexity increases

Engineering Contradiction:
Improveinterfacial and charge defectsVSAvoidprocess steps
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The passivation process is merged with the existing gate dielectric formation step. The same deposition equipment and process conditions used for forming the gate dielectric are utilized to deposit the passivation layer, combining two functions into one process step and avoiding additional process complexity

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces interfacial and charge defects, improves device performance, and maintains broad process windows without adding extra layers, especially beneficial for materials like silicon germanium that have higher defects.

Implementation Method 1

a passivation process using fluorine to reduce dangling bonds and defects in the n-metal work function layer, thereby minimizing aluminum diffusion

Methodology Applied
Scientific EffectPassivation:

Data Source

PatentUS20240363719A1Semiconductor device and method of manufacture
Publication Date: 2024.10.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240363719A1 patent drawing
  • US20240363719A1 patent drawing
  • US20240363719A1 patent drawing

AI summary

Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.