Gate Stack Patterning for 28nm Semiconductor Devices
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Solution Overview
Problem
At the 28 nm technology node, it is challenging to transfer patterns using one-shot exposure with ArF at 193 nm wavelength, leading to non-planarized resist patterns and low oxidation and wet etch resistance due to High-k insulating films and metal electrode materials in semiconductor gate stacks.
Innovation Solution
The process involves etching a cut region between adjacent gate electrodes using a first resist film, followed by removal of the first resist film and subsequent etching of a line & space pattern using a second resist film, improving the planarity of the resist surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one-shot exposure is used for pattern transfer at 28 nm node, then productivity is improved, but manufacturing precision deteriorates due to inability to achieve required pattern dimensions
Solution Approach 1:
The patent applies segmentation by dividing the pattern transfer process into multiple sequential steps: first forming a mandrel pattern, then using it as a template to create the final gate electrode pattern through spacer formation. This multi-step approach achieves the required 28 nm pattern precision that cannot be obtained through one-shot exposure, while maintaining overall productivity through optimized process sequencing.
2Reliability
If High-k insulating film and metal electrode material are used in gate stack, then device performance is improved, but reliability deteriorates due to low oxidation and wet etch resistance
Solution Approach 1:
The patent applies preliminary action by forming a protective spacer structure before performing etching operations on the gate stack. The spacer acts as a pre-established protective layer that prevents oxidation and wet etching damage to the High-k insulating film and metal electrode materials, thereby maintaining their low resistance properties while ensuring process reliability.
Solution Approach 2:
The spacer structure serves as an intermediary element between the etching process and the sensitive gate stack materials. It mediates the interaction by providing a sacrificial layer that protects the High-k insulating film and metal electrode from direct exposure to oxidizing and wet etching environments, thus preserving their electrical properties while enabling successful patterning.
3Manufacturing precision
If resist pattern is formed without planarization, then process complexity is reduced, but manufacturing precision deteriorates due to non-planar resist surface
Solution Approach 1:
The patent applies preliminary action by forming the mandrel pattern and spacer structure before applying the resist material. This pre-structured foundation provides a planarized surface for subsequent resist coating, ensuring uniform resist thickness and pattern accuracy without requiring additional planarization steps during the resist processing stage.
Data Source
AI summary
Provided is a manufacturing method of semiconductor integrated circuit, which is effective when applied to a processing technique for a gate electrode or the like. In the patterning of a gate stack film having a high-k gate insulating film and a metal electrode film in a memory region, etching for a cut region between adjacent gate electrodes is performed first using a first resist film and, after the first resist film that is no longer needed is removed, etching for a line and space pattern is performed using a second resist film.