Gate Stack Trench Capping with Hydrogen Plasma Residue Removal
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more difficult and complex.
Innovation Solution
The method involves forming a semiconductor device structure with a fin structure, isolation layer, dummy gate dielectric and gate layers, and a hydrogen-containing plasma process to remove residues and improve etching efficiency, allowing for the formation of a gate stack and cap layer in a trench, enhancing electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming isolation regions, depositing alternating dielectric and conductive layers, patterning, and etching. Each stage handles specific tasks independently, making the overall complex process more manageable and controllable while enabling continued scaling to smaller feature sizes
Solution Approach 2:
The patent transitions from planar device structures to three-dimensional FinFET structures with vertical channels. This dimensional change increases functional density without proportionally increasing fabrication complexity, as the vertical architecture can be formed using standard deposition and etching processes applied to patterned sacrificial layers
2Area of stationary object
If feature sizes are decreased to increase functional density, then chip area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
Self-aligned processes are employed where each layer is automatically positioned relative to previous layers without additional alignment steps. For example, conductive layers are formed conformally over dielectric layers, and pattern transfer uses the same lithographic masks for multiple features, eliminating cumulative alignment errors and maintaining precision at smaller dimensions
Solution Approach 2:
The patent employs multiple deposition techniques (CVD, PVD, ALD) with controlled thickness parameters to form layers with precise dimensional control. Etch processes use selective chemistry and power parameters to achieve anisotropic etching with vertical sidewalls, maintaining manufacturing precision even as feature sizes decrease
3Device complexity
If conventional etching processes are used, then process simplicity is maintained, but residues remain and etching efficiency decreases
Solution Approach 1:
The etching process parameters are optimized by adjusting plasma power, gas flow rates, and pressure to achieve high etching rates with minimal sidewall damage and residue formation. The patent specifies controlled etch conditions that balance etching speed with surface quality, eliminating the need for complex post-etch cleaning while maintaining process simplicity
Solution Approach 2:
Oxygen plasma or oxygen-containing gases are introduced during or after etching to oxidize and remove carbon-based residues from the etched surfaces. This accelerated oxidation cleanly removes organic contaminants without requiring additional wet cleaning steps, improving etching quality while maintaining process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable semiconductor devices by improving etching processes and reducing residues, thus addressing the complexity of smaller feature sizes and enhancing device performance.
Implementation Method 1
perform a hydrogen-containing plasma process over the gate stack
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.