Gate Stack Profile Control via Selective Etching
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more complex and difficult.
Innovation Solution
A method for forming semiconductor devices involves depositing a gate dielectric layer and a gate electrode layer over a semiconductor substrate, followed by patterning and etching to create multiple gate stacks with controlled profiles, including recessing the lower portions of the gate electrodes to prevent short circuiting and residue formation, using specific etching processes and materials like silicon oxide and high-K dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The gate electrode layer is segmented into multiple portions (first gate electrode portion, second gate electrode portion, third gate electrode portion) with different etching depths. This segmentation allows each portion to be etched to a specific depth using selective etching processes, enabling precise control of gate profiles while managing fabrication complexity at smaller feature sizes
Solution Approach 2:
Different regions of the gate electrode structure are given different properties through selective etching. The first gate electrode portion is etched to a first depth, the second to a second depth, and the third to a third depth, creating local variations in gate electrode depth that optimize device performance while maintaining controllability in the fabrication process
2Reliability
If gate electrodes are etched to form multiple gate stacks, then device functionality is improved, but short circuiting and residue formation between adjacent gate electrodes may occur
Solution Approach 1:
The selective etching process is designed to prevent short circuiting and residue formation before they can occur. By controlling the etching depth of each gate electrode portion separately and using appropriate etching selectivity between different materials (gate dielectric layer, first gate electrode layer, second gate electrode layer), the process preemptively avoids the formation of harmful residues and short circuits between adjacent gate stacks
Solution Approach 2:
The etching parameters are changed and optimized for different gate electrode portions. Different etching depths (first depth, second depth, third depth) and different etching selectivities are applied to remove the gate dielectric layer and etch the gate electrode layers to controlled extents, preventing harmful effects while achieving the desired gate stack structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the quality and reliability of semiconductor devices by preventing short circuiting and residue formation between adjacent gate electrodes, allowing for precise control of gate electrode profiles and enhancing the complexity and efficiency of semiconductor device fabrication at smaller scales.
Implementation Method 1
depositing a gate dielectric layer and a gate electrode layer over a semiconductor substrate
Implementation Method 2
depositing a gate dielectric layer and a gate electrode layer over a semiconductor substrate
Implementation Method 3
followed by patterning and etching to create multiple gate stacks with controlled profiles
Data Source
AI summary
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.