Gate Stack Recess Capping After Hydrogen Plasma Cleaning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more difficult and complex.
Innovation Solution
The method involves forming a semiconductor device structure with a fin structure, isolation layer, dummy gate dielectric layer, and gate stack, including a hydrogen-containing plasma process to remove residues and enhance electrical properties, and a cap layer to prevent shorting, while using stressors to apply stress to the channel region for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty and complexity increase
Solution Approach 1:
The fabrication process is divided into multiple specialized stages including forming isolation regions, creating fin structures, depositing dummy gate dielectric layers, forming gate stacks, and applying stressors. Each stage addresses specific requirements independently, making the overall complex process more manageable and controllable despite small feature sizes
Solution Approach 2:
Dummy gate dielectric layers are formed in advance before the actual gate structure is created. These preliminary structures serve as placeholders and guides for subsequent processing steps, enabling better control over final device geometry and reducing process complexity
2Productivity
If feature sizes are decreased to increase functional density, then chip area utilization is improved, but manufacturing reliability deteriorates
Solution Approach 1:
Different regions of the device receive different treatments: isolation layers are selectively formed in specific regions, stressors are applied locally to channel regions, and gate stacks are positioned precisely over active areas. This localized approach ensures high reliability in critical regions while maintaining high functional density
Solution Approach 2:
Isolation layers are formed beforehand to electrically isolate adjacent devices and prevent unwanted interactions. This preliminary isolation structure cushions against potential reliability issues that could arise from device cross-talk or leakage currents in densely packed configurations
3Reliability
If hydrogen-containing plasma process is used to remove residues, then electrical properties are improved, but process time and complexity increase
Solution Approach 1:
The plasma process uses hydrogen-containing gas to chemically react with and remove carbon residues from the gate stack surface. By changing the chemical composition of the plasma environment, the process efficiently removes contaminants that would otherwise degrade electrical properties, achieving better device performance despite the additional process step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable semiconductor devices by improving the electrical properties and reliability of the gate stack, facilitating the etching process, and maintaining device performance at smaller scales.
Implementation Method 1
perform a hydrogen-containing plasma process to remove residues of carbon over the gate stack and in the void
Implementation Method 2
perform a hydrogen-containing plasma process to remove residues of carbon over the gate stack and in the void
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.