3D Gate Stack Formation via Sacrificial Layer Etching
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase the integration density of memory devices beyond the limits of planar structures, which requires innovative methods for forming gate structures in semiconductor devices.
Innovation Solution
A method involving the formation of alternately stacked mold insulating and sacrificial layers, crystallization of metal oxide films, and precise etching processes to create vertical structures and conductive layers, enabling the fabrication of advanced gate dielectric and electrode layers in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar structure scaling is continued to increase integration density, then manufacturing complexity and process defects increase beyond acceptable limits
Solution Approach 1:
The patent transitions from planar (2D) memory cell structures to three-dimensional (3D) stacked structures with vertical channel holes and gate electrodes. This dimensional change allows continued scaling and increased integration density without the manufacturing precision degradation that occurs when planar structures are scaled below certain dimensions.
2Reliability
If amorphous metal oxide film is used as gate dielectric and crystallized through heat treatment, then dielectric quality improves but surface layer defects are generated
Solution Approach 1:
The patent extracts or removes the defective surface layer of the crystallized metal oxide film through selective etching processes. This eliminates the surface defects generated during crystallization while preserving the high-quality bulk dielectric layer, thus maintaining reliability without the harmful surface defects.
Solution Approach 2:
The patent employs controlled heat treatment parameters to crystallize the amorphous metal oxide film, followed by selective etching parameters that target only the surface layer. By optimizing these process parameters, the bulk dielectric achieves high crystallinity and quality while the surface defects are removed.
3Shape
If vertical structures are formed through mold structures with sacrificial layers, then 3D gate structures are achieved but process complexity increases
Solution Approach 1:
The patent forms complete mold structures with alternately stacked mold insulating layers and sacrificial layers before forming the vertical channel holes. This preliminary structuring provides precise templates that guide the formation of vertical gates, simplifying the overall process despite the initial complexity of mold formation.
Solution Approach 2:
The sacrificial layers act as intermediaries during the formation process. They are deposited between the mold insulating layers to define the vertical channel holes, and are subsequently removed to create the final gate structure. This intermediary approach enables precise 3D structure formation through sequential processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process defects and facilitates vertical scaling, enhancing the integration density and performance of semiconductor devices by forming efficient gate structures.
Implementation Method 1
crystallizing the metal oxide film
Implementation Method 2
heat-treating the amorphous metal oxide film until the amorphous metal oxide film crystallizes
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings.