Gate Stack Structure with Silicon Formation Layer for Trench Filling
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Solution Overview
Problem
Conventional poly-silicon gates in semiconductor devices face issues such as boron penetration and depletion, leading to reduced gate capacitance and performance, necessitating the use of high-k dielectric layers, which complicates the dual metal gate structure and requires precise thickness and composition control.
Innovation Solution
A manufacturing method involving a gate stack structure with a dielectric layer, gate trench formation, sequential deposition of barrier and work function metal layers, and a silicon formation layer to reduce trench aspect ratio and facilitate conductive layer filling, including the formation of a titanium silicide nitride layer to enhance NMOS efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional poly-silicon gates are used in semiconductor devices, then manufacturing process is simple, but boron penetration and depletion effects occur leading to reduced gate capacitance and performance
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional poly-silicon to metal materials with appropriate work functions. This parameter change eliminates boron penetration and depletion effects while maintaining manufacturing feasibility through established PVD or ALD deposition processes.
Solution Approach 2:
The patent employs composite material structures including metal gate electrodes combined with high-k dielectric layers, and in some embodiments, multi-layer metal structures with different work functions for NMOS and PMOS devices. This composite approach simultaneously improves device performance and enables dual work function requirements.
2Reliability
If high-k dielectric layers are used to replace poly-silicon gates, then gate capacitance and device performance are improved, but dual metal gate structure compatibility and process control become more complicated
Solution Approach 1:
The patent segments the gate structure into distinct functional layers including bottom barrier layers, work function metal layers, and top barrier layers. Each layer performs a specific function, allowing independent optimization and control of thickness and composition parameters for each segment, thereby simplifying overall process control.
Solution Approach 2:
The patent applies local quality by using different material compositions and thicknesses in different regions of the gate structure. For example, different work function metal layers are used for NMOS and PMOS devices, and barrier layer parameters are optimized locally at interfaces with dielectric and semiconductor layers.
3Reliability
If gate trench depth is increased to achieve proper gate structure, then gate control is improved, but aspect ratio of trench increases making conductive layer filling difficult
Solution Approach 1:
The patent performs preliminary actions by forming barrier layers and work function metal layers before filling the conductive layer. The silicon formation layer is deposited and planarized in advance to create a favorable morphology for subsequent conductive layer filling, reducing the effective aspect ratio that the conductive material must navigate.
Solution Approach 2:
The patent addresses the aspect ratio problem by transitioning from a purely vertical filling challenge to a multi-step process that includes lateral planarization. The silicon formation layer provides a lateral platform that facilitates conductive layer deposition, effectively solving the high aspect ratio filling difficulty through dimensional approach change.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the filling of conductive layers in high-aspect-ratio trenches, reduces manufacturing complexity, and enhances the performance and efficiency of NMOS devices by controlling trench depth and aspect ratio, while forming a titanium silicide nitride layer that lowers threshold voltage.
Implementation Method 1
the silicon generating layer reacts with the top barrier layer to form a titanium silicide nitride layer
Data Source
AI summary
The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.