Gate Stack Spacer Formation for Semiconductor Devices
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Solution Overview
Problem
The scaling down of semiconductor devices makes it increasingly difficult to fill high-K dielectric and metal gate conductors in small gaps, leading to degradation of the gate stack configuration, which is exacerbated by short channel effects.
Innovation Solution
A replacement spacer process is introduced, where source and drain regions are formed using shielding layers, allowing the gate stack, including a gate conductor formed as a spacer on the sidewall of a dielectric layer, to be constructed in a larger space, facilitating easier formation and reducing the challenges of filling small gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the replacement gate process is used to fill high-K dielectric and metal gate conductor in a gap between gate spacers, then the gate stack configuration can be achieved, but it becomes increasingly difficult to fill the materials in small gaps due to device scaling down
Solution Approach 1:
The patent inverts the conventional replacement gate process by forming the gate conductor as a spacer on the sidewall of a dielectric layer rather than filling the gate dielectric into a pre-formed gap. This inversion transforms the difficult gap-filling step into a simpler spacer formation process, resolving the manufacturing difficulty while maintaining gate stack precision
Solution Approach 2:
The patent transitions from a planar gap-filling approach to a three-dimensional spacer formation approach. By forming the gate conductor as a vertical spacer on the sidewall of the dielectric layer, the process exploits the third dimension (vertical height) to avoid the limitations of horizontal gap filling, thereby easing manufacturing while achieving precise gate stack configuration
2Productivity
If device scaling continues to reduce feature sizes, then device density increases, but short channel effects become more significant and degrade gate stack performance
Solution Approach 1:
The patent performs preliminary actions by forming the gate conductor spacer and dielectric layer structure before final gate stack completion. This preliminary structuring establishes a robust foundation that maintains gate control over the channel, thereby mitigating short channel effects while enabling continued device scaling and high density
Data Source
AI summary
Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.